數(shù)字電路課程設(shè)計(jì)

1、 數(shù)字電路課程設(shè)計(jì)一 設(shè)計(jì)思路：對(duì)工業(yè)控制中生產(chǎn)軋鋼板厚度的測(cè)量，設(shè)計(jì)一個(gè)通過移動(dòng)的滑動(dòng)電阻，測(cè)量其在電路中的電壓變化，再通過單片機(jī)等判斷厚度，進(jìn)行軋鋼機(jī)的調(diào)整。做一個(gè)電壓測(cè)量器，數(shù)據(jù)采樣通過數(shù)據(jù)分配器輸入ADC0809數(shù)模轉(zhuǎn)換器，通過ADC0809轉(zhuǎn)換為數(shù)字信號(hào)，并通過數(shù)碼管顯示十六進(jìn)制顯示。二 設(shè)計(jì)內(nèi)容：模數(shù)轉(zhuǎn)換器ADC0809 程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity ADC0809 is port ( d

2、: in std_logic_vector(7 downto 0); -ADC0809輸出的采樣數(shù)據(jù) clk,eoc : in std_logic; -clk為系統(tǒng)時(shí)鐘，eoc為ADC0809轉(zhuǎn)換結(jié)束信號(hào)clk1,start, ale,en: out std_logic; -ADC0809控制信號(hào) abc_in :in std_logic_vector(2 downto 0); -模擬選通信號(hào)abc_out :out std_logic_vector(2 downto 0); -ADC0809模擬信號(hào)選通信號(hào) q : out std_logic_vector(7 downto 0); -送至8

3、個(gè)并排數(shù)碼管信號(hào) end ADC0809; architecture behav of ADC0809 is type states is ( st0,st1, st2, st3, st4,st5,st6); -定義各狀態(tài)的子類型signal current_state, next_state:states:=st0;signal regl :std_logic_vector(7 downto 0); -中間數(shù)據(jù)寄存信號(hào)signal qq:std_logic_vector(7 downto 0):="00000000"begincom:process(current_sta

4、te,eoc) -規(guī)定各種狀態(tài)的轉(zhuǎn)換方式begin case current_state is when st0=>next_state<=st1;ale<='0'start<='0'en<='0' when st1=>next_state<=st2;ale<='1'start<='0'en<='0' when st2=>next_state<=st3;ale<='0'start<='1

5、9;en<='0' when st3=> ale<='0'start<='0'en<='0' if eoc='1' then next_state<=st3; -檢測(cè)EOC的下降沿 else next_state<=st4; end if; when st4=> ale<='0'start<='0'en<='0' if eoc='0' then next_state<=st4; -

6、檢測(cè)EOC的上升沿else next_state<=st5;end if; when st5=>next_state<=st6;ale<='0'start<='0'en<='1' when st6=>next_state<=st0;ale<='0'start<='0'en<='1'regl<=d; when others=> next_state<=st0;ale<='0'start<=&

7、#39;0'en<='0' end case;end process;clock:process(clk) -對(duì)系統(tǒng)時(shí)鐘進(jìn)行分頻，得到ADC0809轉(zhuǎn)換工作時(shí)鐘begin if clk'event and clk='1' then qq<=qq+1; -在clk1的上升沿，轉(zhuǎn)換至下一狀態(tài)if QQ="11111111" THEN clk1<='1' current_state <=next_state; elsif qq<="01111111" then clk

8、1<='0' end if; end if;end process;q<=regl; abc_out<=abc_in; end behav; 1， 生成的工程編譯：2，生成的原理圖：3，RTL級(jí)電路：2， 仿真時(shí)序圖：說明：設(shè)置clk信號(hào)，選擇通道進(jìn)行模擬信號(hào)作為輸入進(jìn)行A/D轉(zhuǎn)換，sen信號(hào)為高電平時(shí)，ADC0809將8位數(shù)據(jù)送至Q輸出。.八選一數(shù)據(jù)分配器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY select1_8 IS PORT(Q:IN STD_LOGIC; sel: IN STD_LOGIC_VE

9、CTOR(2 DOWNTO 0); D:OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );END select1_8;ARCHITECTURE abc OF select1_8 IS -81數(shù)據(jù)分配器 BEGIN PROCESS(sel) -進(jìn)程語言使用 BEGIN CASE sel IS -使用case語句 WHEN "000"=> D(0)<=Q; WHEN "001"=> D(1)<=Q; WHEN "010" => D(2)<=Q; WHEN "011"

10、;=> D(3)<=Q; WHEN "100"=> D(4)<=Q; WHEN "101" => D(5)<=Q; WHEN "110"=> D(6)<=Q; WHEN OTHERS=>D(7)<=Q; END CASE; END PROCESS;END abc;1，通過編譯產(chǎn)生正確的8選一數(shù)據(jù)分配器項(xiàng)目：,2，通過建立原理圖產(chǎn)生原理圖八選一數(shù)據(jù)分配器：Sel輸入選擇的信號(hào)，Q為輸入數(shù)據(jù)引腳，D7.0為分配時(shí)輸出輸入的數(shù)據(jù)Q的引腳。3， 生成的RTL級(jí)電路4，數(shù)據(jù)分配器的時(shí)序

11、仿真波形：設(shè)置Q為隨機(jī)的1,0信號(hào)輸入，sel為二進(jìn)制000111循環(huán)的選擇信號(hào)，D0D7為輸出信號(hào)，仿真中有延時(shí)的原因，部分輸出收到上一狀態(tài)的影響。led7段數(shù)碼管：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity ymp is port(num:in std_logic_vector(3 downto 0);seg_r:out std_logic_vector(7 downto 0);end ymp;architecture

12、 a1 of ymp isbeginprocess(num)begincase num iswhen "0000" => seg_r <= "11000000" -1when "0001" => seg_r <= "11111001" -2when "0010" => seg_r <= "10100100" -3when "0011" => seg_r <= "10110000" -4wh

13、en "0100" => seg_r <= "10011001"when "0101" => seg_r <= "10010010"when "0110" => seg_r <= "10000010" -.when "0111" => seg_r <= "11111000"when "1000" => seg_r <= "10000000"

14、;when "1001" => seg_r <= "10010000"when "1010" => seg_r <= "10001000"when "1011" => seg_r <= "10000011"when "1100" => seg_r <= "10100110"when "1101" => seg_r <= "10100001"

15、;when "1110" => seg_r <= "10000110" -fwhen "1111" => seg_r <= "10001110" -0end case;end process;end a1;仿真：Num輸入，seg_r輸出相應(yīng)的16進(jìn)制RTL級(jí)電路6.例化設(shè)計(jì)頂層元器件：頂層設(shè)計(jì)：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.a

16、ll;entity lihua isport ( -頂層文件對(duì)于引腳的聲明定-義 d:in std_logic; -數(shù)據(jù)輸入引腳 s:in std_logic_vector(2 downto 0); -分配選通引腳 led1 : out std_logic_vector(7 downto 0); led2 : out std_logic_vector(7 downto 0); clk,eoc : in std_logic -時(shí)鐘和使能 );end lihua;architecture structure of lihua iscomponent select1_8 -八選一數(shù)據(jù)分配器元件聲明

17、port ( Q:IN STD_LOGIC; sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); end component; component ADC0809 port ( d : in std_logic_vector(7 downto 0); -ADC0809輸出的采樣數(shù)據(jù) clk,eoc : in std_logic; -clk為系統(tǒng)時(shí)鐘，eoc為ADC0809轉(zhuǎn)換結(jié)束信號(hào)clk1,start, ale,en: out std_logic; -ADC0809控制信號(hào) abc_in :i

18、n std_logic_vector(2 downto 0); -模擬選通信號(hào)abc_out :out std_logic_vector(2 downto 0); -ADC0809模擬信號(hào)選通信號(hào) q : out std_logic_vector(7 downto 0); end component;component ymp -數(shù)據(jù)分配器 port( num:in std_logic_vector(3 downto 0); seg_r:out std_logic_vector(7 downto 0);end component;signal a:std_logic_vector(2 downto 0); -中間信號(hào)的聲明signal b:std_logic_vector(7 downto 0);signal d1:std_logic_vector(3 downto 0);signal d2:std_logic_vector(3 downto 0);begin -引腳的聲明，調(diào)用u0:ADC0809 port map(d=>b,clk=>clk,eoc=>eoc,abc_in=>s,q(0)=>d1(0),q(1)=>d1(1),q(2)=