外文翻譯---觸發(fā)器

1、.英文資料及中文翻譯FLIP-FLOPS1 IntorduceIn this passage, we show how to design flip-flops, which operate as one-bit memory cells. Flip-flops are also called latches. Logic circuits constructed using flip-flops can have the present output be a function of both the past and present inputs. Such circuits are ca

2、lled senfiential logic circuits. All flip-flops are based on the same principle: Positive feedback is used to produce a circuit that is bistable . A bistable circuit is one that has two stable operating points. Which operating point the circuit is in is called the state of the circuit. If the state

3、can be sensed and changed, then the circuit can function as a one-bit memory element. The simplest bistable circuit is constructed using two inverters in a loop as shown in Figure 11.This circuit only has two nodes, A and B. Because of the inverters, if A is high, B must be low and vice versa; hence

4、, the circuit has two stable states. The operation of the bistable circuit can also be viewed using a plot of the transfer characteristic of the two inverters in series, as shown in Figure 12. Part (a) of the figure shows the static transfer characteristic of one of the inverters. When the input vol

5、tage is below the threshold (a logical ZERO), the output voltage is high (a logical ONE). When the input voltage is greater than the threshold, the output voltage is low. In part (b) of the figure, we show the transfer characteristic that results from putting both inverters in series. Any solution o

6、f the equations for this circuit must also lie on this characteristic. Because of the external connection, the input and output voltages of the series connection of the two inverters must be the same. Therefore, we draw a line with a slope of unity on the plot as well. This line is called the load l

7、ine, because it represents the external load connection for the two inverters in series. Any solution of the equations for this circuit must also lie on the load line. Therefore, when the equations are simultaneously solved, the only possible operating points are found where the straight line inters

8、ects the transfer characteristic. There are three intersections on the plot, but only two of them are stable, as we will now demonstrate.The point where the load line intersects the middle of the transfer characteristic is not stable. To see that this statement is true, suppose for the moment that t

9、he circuit is at this point. If the input voltage increases at all (due to noise or some change in the circuit), the output voltage of the inverters must also increase. But the output is input, so as it increases, it causes further increases in the output, and the original change is magnified. This

10、positive feedback will quickly drive the circuit to the top operating point shown. At that point, the input and output of the two-inverter chain are high and the midpoint (B in Figure 11) is low, so the circuit is stable and can remain in this state forever. If we started at the midpoint and let the

11、 input voltage decrease a bit, we would end up at the lower operating point, which is again stable.In the sections that follow, we show how we can move this bistable circuit from one operating point to the other. The internal positive feedback will then hold the circuit at that state until we delibe

12、rately change it; hence, the circuit has memory.Figure 11A bistable circuit(a)(b)Figure 12 (a) One inverter and its transfer characteristic (b) The transfer characteristic for two inverters in series and the load line for the circuit 2 The Set-Reset Flip-FlopA set-reset (SR) flip-flop is shown in Fi

13、gure 21(a). A table describing the function of the circuit is shown in part (b) of the figure, and the schematic symbol is shown in part (c). This function table is similar to a truth table, but it describes a dynamic situation, not a static one. The output is the output at some discrete time, denot

14、ed by Qn, and the table includes an entry for the previous state of the flip-flop (Qn-1). Although the circuit is drawn differently, the two NOR gates are in series, just like the inverters in Figure 12(b). The configuration shown here is usually described as cross coupled. The flip-flop has two out

15、puts that are complements of each other. We usually consider the Q output to be the state of the flip-flop.(a)SRQn00Qn-101010111不允許的（b）(c) Figure 21 (a) An SR flip-flop, (b) a table describing the circuits function (c) the schematic symbol.The circuit operates in the following way: If both inputs (S

16、 and R) are zero, the previous state is retained. Suppose, for example, that Qn-1 is high (i.e., ONE). Then the output of the bottom NOR, which isn-1 , will be low (i.e., ZERO), independently of what S is. In this case, both inputs to the top NOR are low, so its output is high, as originally assumed

17、. Now suppose that Qn-1 is low. In this case, both inputs to the bottom NOR are low, so n-1 is high. Therefore, the output of the top NOR, Qn-1, will be low, as assumed. Now consider what happens when the set input, S, goes high while R remains low. The output of the bottom NOR, n-1 , will now go lo

18、w, independent of what the previous state of the circuit was. With R low as well, this guarantees that Qn will go high (i.e, the flip-flop has been “set”). Note that S does not have to stay high. Once the flip-flop is set, the S input can go low again, and the state will be retained. This sequence o

19、f events is illustrated in Figure 22 The figure shows that there is some delay through each gate, so it takes a time td for the change at the gate input to affect its output. Figure 22 A timing diagram for the SR flip-flop. The arrows indicate which transition causes the following change.The operati

20、on of the reset input is similar. If R goes high while S is kept low, the output of the top NOR, Qn, will go low (i.e., the flip-flop is “reset”). With Qn and S both low, the bottom NOR output will be high. The reset input can go low again, and this new state will be retained. This sequence is also

21、illustrated in Figure 22.Finally, we note that both inputs should not be allowed to go high at the same time. If this happens, both NOR outputs go low, so Q and are not complements anymore. Also, if both inputs are high and then go low at exactly the same time, we cant predict what the resulting out

22、put state will be, since both outputs will try to go high, which is a condition that cannot be sustained. Which output will actually stay high depends on mismatches in the NOR gates and cannot be predicted.3 The JK Flip-FlopThe fact that the output of an SR flip-flop is undefined if both inputs go h

23、igh is troublesome in many applications. The JK flip-flop avoids this problem and is more flexible in its operation. The JK flip-flop is a clocked flip-flop; that is, it requires a separate clock input to operate. This clock signal is usually a square wave with a fixed period. Logic circuits that re

24、quire a clock and that only allow output transitions to occur in synchrony with the clock are called synchronous-logic circuits. The clock can be generated using an astable multivibrator. (a) (b)JKQn00Qn-101010111n-1 (c) Figure 31 (a) A JK flip-flop made using an SR flip-flop. (b) The Schematic symb

25、ol for a JK flip-flop (c) the function table. (The flip-flop only changes state when the clock is high.)A JK flip-flop is shown in Figure 31(a); the schematic symbol is shown in part (b) of the figure, and the function table is shown in part (c). The AND gates serve to enable the inputs to the SR fl

26、ip-flop. That is, only when the clock is high are the J and K inputs able to affect the SR flip-flop. In addition to needing the clock to be high, the J input affects S only if the SR flip-flop is currently reset, and the K input affects R only if the flip-flop is currently set. Therefore, we see th

27、at when both J and K are low, S and R will be low, and the flip-flop will hold its present state just like the SR flip-flop. When J is high and the flip-flop is currently reset (i.e., n-1 is high), the flip-flop will be set when the clock goes high, independently of what K is. If K is high and the f

28、lip-flop is currently set (i.e., Qn-1 is high), the flip-flop will reset when the clock goes high, independently of what J is. It follows that if both J and K are high, the flip-flop will toggle its state when the clock goes high. When operated in the toggle mode, a JK flip-flop is sometimes called

29、a T flip-flop.The JK flip-flop as shown in Figure 31has a major problem: It will work only if the clock pulse width (i.e., the time the clock is high) is short compared with the propagation delay of the gate. To understand this limitation, consider what happens when J and K are both high and Qn-1 is

30、 low. In this case, the output of the flip-flop will toggle when the clock goes high, as indicated in the function table. But, if the output toggles and the clock is still high, the output will toggle again . This process will repeat until either the clock goes low or J or K changes. In order to avo

31、id this problem, we use master-slave JK flip-flop.A master-slave JK flip-flop is shown in Figure 32. The master flip-flop is enabled when the clock is high, so the data are latched into the master during that portion of the clock cycle. During that time, c is low and the slave is disabled and holds

32、the previous value. Then the clock goes low, c goes high and enables the slave. The data from the master are then transferred to the slave and show up at the output. Since the master and slave flip-flops are never enabled at the same time, the output will not continue to toggle if the clock is held

33、in any one state for too long. The clock does have to remain in each state long enough to allow for the propagation delay through one of the flip-flops.Figure 32 A master-slave JK flip-flopIn designing a master-slave JK flip-flop, we must carefully consider the propagation delays of the individual g

34、ates to prevent the slave from changing before it should. For example, in the figure, the data on SM and RM can change one gate delay after the clock goes high. The slave clock, which is c, goes low one inverter delay after the clock goes high. We must be sure that the slave clock changes before the

35、 output of the master flip-flop can change; otherwise, the data will pass on through to the slave and we will not have accomplished our purpose. Similarly, when the clock goes low, we must be sure that the master is disabled before the slave outputs can change.The JK flip-flop just described is leve

36、l-triggered flip-flop; that is, the master is enabled when the clock level is high, and the slave is enabled when the clock level is low. The problem with level-triggered JK flip-flops is that they are sensitive to glitches on the inputs at certain points in the operation. For example, suppose that

37、the previous state of the flip-flop was Q=0 and that we are now ready for the next clock cycle. Suppose further that J=0 and K=1, so we are resetting the flip-flop again; in other words, we dont want the state to change. In this case, while the clock is high, both SM and RM are low, so the master fl

38、ip-flop output should not change. However, if a positive glitch occurs on the J input prior to the clock going low, it can pass through to SM and set the master flip-flop. Since Q is low, the AND gate driving RM is disabled, so we dont have any opportunity for the flip-flop to be reset. As a result,

39、 when the clock goes low, this error will be passed on to the slave. A similar situation exists if we are trying to set the flip-flop when it is already set. A positive glitch on the K input can cause an erroneous reset. This problem is sometimes called ones catching, since the flip-flop has capture

40、d an erroneous ONE. We could make the problem far less likely to occur if we used a clock with a very short positive pulse, but a much better solution is to use an edge-triggered JK flip-flop.An edge-triggered JK flip-flop is shown in Figure 33(a), and the schematic symbol is shown in part (b) of th

41、e figure. The triangle inside the block in part (b) indicates that the flip-flop is edge-triggered. as explained in a moment, and the bubble indicates that it is negative edge triggered (i.e., the input is latched on the negative-going edge of the clock ). (a) (b) Figure 33 (a) An edge-triggered JK

42、flip-flop (b) the schematic symbol for it To understand how this circuit operates, we need to first examine the input gate structure. Consider, for example, the situation where Q=0 and we want to set the flip-flop, so J=1. Part of the input structure is shown in Figure 34(a) for this case, and the c

43、orresponding waveforms are shown in part (b) of the figure. (a) (b) Figure 34(a) A part of the input circuit when Q=0. (b) The resulting waveforms.The bubbles at the input of the second gate invert the inputs so that the AND is true when both inputs are low. Because Q=0, we know that =1. Now, with J

44、=1, the output of the NAND gate, Jc, will be the inverse of the clock, delayed by one gate delay. Therefore, when the clock goes low, Jc will go high one gate delay later, as shown. During that gate delay, both inputs to the second gate are low, so the AND is true and S goes high. In other words, th

45、e negative edge of the clock has produced a narrow pulse on the S line as a result of the J input being high. Similarly, if the K input is high and Q=1, a negative clock edge will produce a narrow pulse on the R line. In this way, the SR flip-flop is set or reset only on the negative clock edge. As

46、long as the J and K inputs are held constant for some short time prior to the clock edge (called the setup time) and are held constant for some short time after the clock edge (called the hold time), the circuit is insensitive to glitches on the inputs. It is also possible to make positive edge-trig

47、gered circuits4 The D Flip-FlopA D flip-flop is shown is Figure 41(a), and its schematic symbol is shown in part (b) of the figure. This flip-flop implements a digital delay; that is, the output at the end of each clock cycle is equal to the input on the previous cycle, as seen in the function table

48、 in part (c) of the figurehence the name D flip-flop. This particular circuit is positive-edge triggered, so the output changes state slightly after the positive-going edge of the clock. The output is insensitive to the value of the D input, except for a brief time before (the setup time) and after

49、(the hold time) the positive clock edge. D flip-flips are commonly used in shift registers and counters, as discussed in the next section. (a) (b)Dn-1Qn0011 (c) Figure 41 (a) A D flip-flop (b) its schematic symbol (c) the function table. Clocked flip-flops also frequently have asynchronous clear and

50、 preset inputs, as shown for a D flop-flop in Figure 42. The preset input will set the flip-flop so that Q=1 at any time, regardless of the state of the clock; that is what is meant by being asynchronous. In similar fashion, the clear input will clear the flip-flop so that Q=0 at any time. Figure 42

51、 A D flip-flop with preset and clear inputs 觸發(fā)器1簡(jiǎn)介本文，我們將介紹如何設(shè)計(jì)可作為一位存儲(chǔ)單元的觸發(fā)器。觸發(fā)器也可稱為鎖存器。采用觸發(fā)器的邏輯電路結(jié)構(gòu)其當(dāng)前的輸出是電路的前一穩(wěn)定狀態(tài)和當(dāng)前穩(wěn)定狀態(tài)的函數(shù)。這樣的電路稱為時(shí)序邏輯電路。所有的觸發(fā)器都遵循同一規(guī)則：正反饋用來(lái)生成雙穩(wěn)態(tài)電路，雙穩(wěn)態(tài)電路是一個(gè)具有兩個(gè)穩(wěn)定工作點(diǎn)的電路。電路所處的工作點(diǎn)稱為電路的一個(gè)狀態(tài)。如果其狀態(tài)能夠讀出和改變，那么此電路就可以作為一個(gè)一位存儲(chǔ)器單元。最簡(jiǎn)單的雙穩(wěn)態(tài)電路是在一個(gè)回路中利用兩個(gè)反相器構(gòu)成的。如圖11所示。這個(gè)電路只有兩個(gè)節(jié)點(diǎn)，A和B。由于是反相器，所以如果A

52、是高電平,那么B就必須是低電平，或者反相。因此，電路具有兩個(gè)穩(wěn)定狀態(tài)。也可以通過(guò)兩個(gè)串聯(lián)的反相器的傳輸特性曲線圖來(lái)查看雙穩(wěn)態(tài)電路的操作，如圖12所示。突12（a）給出了其中一個(gè)反相器的靜態(tài)傳輸特性。當(dāng)輸入電壓低于門限電壓（邏輯0），輸出電壓變?yōu)楦唠娖剑ㄟ壿?）。當(dāng)輸入電壓超過(guò)門限電壓，則輸出為低電平。在圖12（b），給出了將兩個(gè)反相器串聯(lián)后所得到的傳輸特性曲線。該電路邏輯等式的任何一個(gè)結(jié)果都必須落在這條特性曲線上。由于是外部連接，兩個(gè)反相器的串聯(lián)連接處的輸入輸出電壓必須相等。因此，再在圖中劃出一條單位斜率的直線。這條線稱為負(fù)載線，因?yàn)樗砹藘蓚€(gè)串聯(lián)反相器的外部負(fù)載的關(guān)系。該電路邏輯等式的任何

53、一個(gè)解也必須落在負(fù)載線上。因此，如果將這兩個(gè)等式聯(lián)立求解，就可以得到唯一的工作點(diǎn)，這一點(diǎn)正是負(fù)載直線與傳輸特性曲線的交點(diǎn)。在圖中的曲線上一共有三個(gè)交點(diǎn)，但是只有其中兩個(gè)是穩(wěn)定的，正如我們將要論證的。圖 11雙穩(wěn)態(tài)電路 (a) （b） 圖 12（a）反相器和它的傳輸特性 （b）兩個(gè)反相器串聯(lián)的傳輸特性和負(fù)載曲線負(fù)載直線與傳輸特性曲線中部的交點(diǎn)是不穩(wěn)定的。為了證明這點(diǎn)，假設(shè)在某一時(shí)刻電路工作與這一點(diǎn)。如果無(wú)論何時(shí)輸入電壓增加了（由于噪聲或是電路發(fā)生一些變化），反相器的輸出電壓也必須增大。但是由于輸出就是輸入，因此它的增大會(huì)導(dǎo)致輸出的進(jìn)一步增加，原有的變化被放大了。這樣的正反饋將迅速驅(qū)動(dòng)電路達(dá)到所示

54、的頂端的工作點(diǎn)。在那一點(diǎn)，二反相器鏈的輸入輸出電壓都很高，而中間點(diǎn)電壓（圖11中的vB）較低。因此電路是穩(wěn)定的并且能夠永遠(yuǎn)保持著狀態(tài)。如果從中間點(diǎn)開始讓輸入電壓減小一點(diǎn)，那么會(huì)落在更低的工作點(diǎn)上，再次達(dá)到穩(wěn)定。在接下來(lái)的部分，我們將說(shuō)明如何使這個(gè)雙穩(wěn)態(tài)電路從一個(gè)工作狀態(tài)轉(zhuǎn)移到另一個(gè)工作狀態(tài)，但是，內(nèi)部的正反饋將會(huì)使電路保持在這個(gè)狀態(tài)直到有意改變它。因此電路具有記憶。2 SR觸發(fā)器SR（設(shè)置-復(fù)位）觸發(fā)器如圖21（a）所示。圖21（b）給出了電路的功能表，而圖21(c)給出了它的電路邏輯符號(hào)。這個(gè)功能表與真值表類似，但它描述的是動(dòng)態(tài)的情況，而不是靜態(tài)的。其輸出是在一些離散時(shí)間上的輸出，用Qn表示

55、，此外表中還包括觸發(fā)器前一狀態(tài)的輸入(Qn-1)。雖然所畫的電路與上節(jié)所講得不相同，但它也是兩個(gè)或非門串聯(lián)在一起，就像圖12(b)中的兩個(gè)反相器一樣。這里所示的結(jié)構(gòu)通常也被描述為交叉耦合。觸發(fā)器的兩個(gè)輸出是互補(bǔ)的。我們通常認(rèn)為輸出Q是觸發(fā)器的狀態(tài)。(a)SRQn00Qn-101010111不允許的 （b） (c) 圖 21 (a) SR觸發(fā)器 （b）描述電路的功能表 （c）電路邏輯符號(hào)該電路的工作原理如下：如果兩個(gè)輸入端(S和R)都是邏輯0，則保持前一狀態(tài)。例如，假設(shè)Qn-1時(shí)高電平（即邏輯1），那么無(wú)論S是什么狀態(tài)，下面那個(gè)或非門的輸出 n-1 都將是低電平(即邏輯0)。在這種情況下，上面那

56、個(gè)或非門的兩個(gè)輸入端都是低電平，因此它的輸出是高電平，正如前面所假設(shè)的那樣?，F(xiàn)在，我們假設(shè)Qn-1是低電平。在這種情況下，下面那個(gè)或非門的兩個(gè)輸入都是低電平，所以其輸出 n-1 為高電平。因此，上面那個(gè)或非門的輸出Qn-1就像假設(shè)的那樣是低電平?，F(xiàn)在考慮當(dāng)置1端S為高電平而置0端R保持低電平時(shí)會(huì)發(fā)生什么情況。這時(shí)無(wú)論電路的前一狀態(tài)是怎樣的，下方的或非門的輸出 n-1 都將變?yōu)榈碗娖健Ｔ偌由蟁也是低電平，這就保證了Qn將變?yōu)楦唠娖剑从|發(fā)器被置位為1）。注意，S不必一直處于高電平，一旦觸發(fā)器被置1，輸入端S便可再次回到低電平，狀態(tài)將被保持。整個(gè)過(guò)程的順序在圖22中用圖解進(jìn)行了說(shuō)明。從圖中可以看到，在通過(guò)每一個(gè)門時(shí)都有一定的延時(shí)。因此，在門輸入端的變化需要延遲一個(gè)時(shí)間td才能影響到輸出端。 圖22 SR 觸發(fā)器的時(shí)序圖 箭頭表明此處輸入電平的轉(zhuǎn)換引起的隨后輸出的變化置0輸入端的工作原理是類似的。如果R達(dá)到高電平而S保持而低電平，那么上面那個(gè)或非門的輸出Qn將變?yōu)榈碗娖剑从|發(fā)器被置0）。由于Qn和S都為低電平，下方的或非門的輸出將為高電平。此時(shí)置0端可以再次回到低電平，新的狀態(tài)將被保持。其順序在圖2