嵌入式CISC模型機(jī)設(shè)計(jì)

1、目錄1：課程設(shè)計(jì)題目12：嵌入式CISC模型機(jī)數(shù)據(jù)通路框圖13：操作控制器的邏輯框圖14：模型機(jī)的指令系統(tǒng)和所有指令的指令格式25：所有機(jī)器指令的微程序流程圖或CPU操作流程圖36: 操作控制器單元47：嵌入式CISC模型計(jì)算機(jī)的頂層電路圖68：匯編語言源程序69：機(jī)器語言源程序710：機(jī)器語言程序的功能仿真波形圖及結(jié)果分析811：進(jìn)行時(shí)序仿真是芯片的引腳分配812：故障現(xiàn)象和故障分析813：軟件清單，含各個(gè)部件的VHDL源程序(.VHD)或圖形描述文件(.gfd)813.1:ALU單元813.2: 狀態(tài)條件寄存器單元1113.3: 暫存寄存器單元1213.4: 3選1數(shù)據(jù)選擇器1313.5：

2、5選1數(shù)據(jù)選擇器1413.6: 程序計(jì)數(shù)器單元1513.7: 地址寄存器單元1713.8: 主存儲(chǔ)器單元1713.9: 指令寄存器單元1813.10: 時(shí)序產(chǎn)生器單元1913.11: 微程序控制器單元2013.11.1: 地址轉(zhuǎn)移邏輯電路2113.11.2: 微地址寄存器2313.11.3: 微地址轉(zhuǎn)換器2513.11.4: 控制存儲(chǔ)器2613.11.5: 微指令寄存器2813.11.6: 微地址轉(zhuǎn)換器3013.11.7: 指令代碼轉(zhuǎn)換器31311：課程設(shè)計(jì)題目設(shè)計(jì)一臺(tái)嵌入式CISC模型計(jì)算機(jī)：采用定長CPU周期、聯(lián)合控制方法，并完成一定功能的機(jī)器語言源程序進(jìn)行驗(yàn)證，機(jī)器語言源程序功能如下：輸

3、入5個(gè)有符號(hào)整數(shù)（8位二進(jìn)制補(bǔ)碼表示），求所有正數(shù)的平方和并輸出顯示。2：嵌入式CISC模型機(jī)數(shù)據(jù)通路框圖模型機(jī)由CISC微處理器、地址寄存器AR、ROM存儲(chǔ)器組成。微處理器有算數(shù)邏輯單元ALU、狀態(tài)條件寄存器、累加器AC、數(shù)據(jù)暫存器R、通用寄存器R0R3、程序計(jì)數(shù)器PC、指令寄存器IR、操作控制器和時(shí)序產(chǎn)生器組成。模型機(jī)數(shù)據(jù)通路如圖2-1所示：圖2-1 模型機(jī)數(shù)據(jù)通路框圖說明：外部時(shí)鐘信號(hào)上邊沿有效。3：操作控制器的邏輯框圖微程序控制器主要由控制存儲(chǔ)器、微指令寄存器和地址轉(zhuǎn)移邏輯電路三大部分組成，其中微指令寄存器分為微地址寄存器和微命令寄存器兩部分。微程序控制器在T4內(nèi)形成微指令的微地址，并

4、訪問控制存儲(chǔ)器，在T2的上邊沿到來時(shí)，將讀出的微指令打入微指令寄存器，即圖中的微命令寄存器和微地址寄存器。微程序控制器組成原理框圖如下圖3-1所示。圖3-1 微程序控制器組成原理框圖4：模型機(jī)的指令系統(tǒng)和所有指令的指令格式為了完成求和功能，系統(tǒng)設(shè)計(jì)了9條指令：IN（輸入指令），MOV（將一個(gè)數(shù)送入寄存器），CMP（完成比較功能），JB（小于等于跳轉(zhuǎn)），ADD（兩數(shù)相加），DEC（自減1），JMP（無條件跳轉(zhuǎn)），MUL(兩數(shù)相乘)，OUT（輸出）。助記符號(hào)指令格式功 能IN Rd 1 0 0 0××Rd將數(shù)據(jù)存到Rd寄存器OUT Rs1 1 1 1Rs××

5、(Rs)LEDADD Rs,Rd1 1 0 0××Rd(Rs)+(Rd) RdCMP Rs,Rd1 0 1 0RsRd(Rs)-(Rd),鎖存CY和ZIDEC Rd1 1 0 1××Rd(Rd)+1RdMOV Rd,data1 0 0 1××RddatadataRdJMP addr1 1 1 0××××addraddrPCJB addr1 0 1 1××××addr若小于，則addrPCMUL Rs,Rd0001RsRd(Rs)*(Rd)Rd說明：對(duì)Rs和

6、Rd的規(guī)定：Rs或Rd選定的寄存器0 0R00 1R11 0R21 1R3模型機(jī)規(guī)定數(shù)據(jù)的表示采用定點(diǎn)整數(shù)補(bǔ)碼表示，單字長為8位，其格式如下：76 5 4 3 2 1 0符號(hào)位尾數(shù)5：所有機(jī)器指令的微程序流程圖或CPU操作流程圖微程序控制器的設(shè)計(jì)過程如下：（1）根據(jù)指令格式和指令系統(tǒng)設(shè)計(jì)所有機(jī)器指令的微程序流程圖，并確定每條微指令的微地址和后繼微地址；（2）設(shè)計(jì)微指令格式和微指令代碼表；（3）設(shè)計(jì)地址轉(zhuǎn)移邏輯電路；（4）設(shè)計(jì)微程序控制器中的其它邏輯單元電路，包括微地址寄存器、微命令寄存器和控制存儲(chǔ)器；（5）設(shè)計(jì)微程序控制器的頂層電路（由多個(gè)模塊組成）。DECJMPADDJBCMPMOVINMU

7、LFS=1FS=03020071312060F05040316150E0D0C0B0A0908020001PCARPC+1READ MBUSIRP(1)RsLEDPCARPC+1RdBUSBUSACRSBUSBUSACPCARPC+1RsBUSBUSACPCARPC+1SWBUSBUSRdRSBUSBUSACROMBUSBUSPCAC-1BUSBUSRdRdBUSBUSDRRdBUSBUSDRROMBUSBUSRdRdBUSBUSDRP(2)ROMBUSBUSPCAC+DRRdACDR鎖存FC、FZAC*DRRd00000000000000000000OUT6: 操作控制器單元（1）設(shè)計(jì)微指令

8、格式和微指令代碼表CISC模型機(jī)系統(tǒng)使用的微指令采用全水平型微指令，字長為25位，其中微命令字段為17位，P字段為2位，后繼微地址為6位，其格式如下：24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LOAD LDPC LDAR LDIR LDRi RD_B RS_B S1 S0 ALU_B LDAC LDDR WR CS SW_B LED_B LDFR P1 P2 后繼微地址由微指令格式和微程序流程圖編寫的微指令代碼表如下所示，在微指令的代碼表中微命令字段從左邊到右代表的微命令信號(hào)依次為：LOAD、LDPC、LDA

9、R、LDIR、LDRi、RD_B、RS_B、S1、S0、ALU_B、LDAC、LDDR、WR、CS、SW_B、LED_B、LDFR。微地址微命令字段P1P1后繼位地址LOADLDPCLDARLDIRLDRiRD_BRS_BS1S0ALU_BLDACLDDRWRCSSW_BLED_BLDFR00000011100110010011110000000100000011000010001101111000010101000010100101100100101101000100000001110001110010010110000000000001001000001001011111000000101

10、000101100001101100111110000000000011010000010010111110000001110001111000111000001111000000000001000100011100100110100000000000100111100110010011110000000110010101000010001101111000000100001011111001100100111100110000000110010000100011011110000001100011011000001001101111000010010001110111001100100111

11、10000100120011111000010001000110000000000010010100011110000111100000000001001101000110010010110000000000101011000001001011111000010110010110100011111000111100000000010000001000110010010110000000001100001000011001001111000000000（2）設(shè)計(jì)地址轉(zhuǎn)移邏輯電路地址轉(zhuǎn)移邏輯電路是根據(jù)微程序流程圖3-2中的棱形框部分及多個(gè)分支微地址，利用微地址寄存器的異步置“1”端，實(shí)現(xiàn)微地址的多

12、路轉(zhuǎn)移。由于微地址寄存器中的觸發(fā)器異步置“1”端低電平有效，與µA4µA0對(duì)應(yīng)的異步置“1”控制信號(hào)SE5SE1的邏輯表達(dá)式為： SE5=(FC+FZ)P(2)T4SE4=I7P(1)T4SE3=I6P(1)T4SE2=I5P(1)T4SE1=I4P(1)T47：嵌入式CISC模型計(jì)算機(jī)的頂層電路圖在MAX+plus下設(shè)計(jì)的CISC模型機(jī)的頂層電路圖如下圖7-1所示。圖7-1嵌入式CISC模型計(jì)算機(jī)的頂層電路圖8：匯編語言源程序MOV R10 -R1置為0，保存累加結(jié)果 MOV R20 -R2置為0，判輸入數(shù)據(jù)正負(fù)性，計(jì)輸入數(shù)據(jù)的次數(shù) MOV R35 -R3置為5，計(jì)輸入次

13、數(shù) L1: IN R0 -外部輸入數(shù)據(jù)存到R0 DEC R3 -R3減1 CMP R2,R0 -比較R2和R0的大小 JB L2 -若R2小于R0則跳轉(zhuǎn)L2CMP R2,R3 -判斷次數(shù)，若不到5次返回L1JB L1 -跳轉(zhuǎn)到L1JMP L3 -若次數(shù)達(dá)到5次，跳轉(zhuǎn)到L3，輸出結(jié)果，程序結(jié)束L2: MUL R0,R0 - R0大于0，做平方運(yùn)算，存到R0中ADD R0,R1 -R1用來存累加結(jié)果的，故將R0中的平方和R1的值相加CMP R2,R3 -判斷次數(shù)，若不到5次返回L1JB L1 -跳轉(zhuǎn)到L1L3: OUT R1 -將正數(shù)的平方和輸出 9：機(jī)器語言源程序根據(jù)設(shè)計(jì)的指令格式，將匯編語言源

14、程序手工轉(zhuǎn)換成機(jī)器語言源程序，并將其設(shè)計(jì)到模型機(jī)中的ROM中去。與匯編語言源程序?qū)?yīng)的機(jī)器語言源程序如下：助記符 地址（十六進(jìn)制） 機(jī)器代碼 功能MOV1 R0,0 00 10010001 00H R0 01 00000000 MOV1 R1,0 02 10010010 00H R1 03 00000000 MOV1 R2,5 04 10010011 05H R2 05 00000101 L1:IN R0 06 10000000 (SW) R0DEC R3 07 11010011 (R0)-1R3CMP R2,R0 08 10101000 (R2)-(R0)JB L2 09 10110000

15、若小于，L2 PC 0A 00010000 CMP R2,R3 0B 10101011 (R2)-(R3) JB L1 0C 10110000 L1PC OD 00000110 JMP L3 0E 11100000 L3PC 0F 00010101L2: MUL R0,R0 10 00010000 (R0)*(R0) R0 ADD R0,R1 11 11000001 (R0)+(R1) R1CMP R2,R3 12 10101011 (R2)-(R3) JB L1 13 10110000 L1PC14 00000110L3: OUT R1 15 11110100 (R1) LED10：機(jī)器語言

16、程序的功能仿真波形圖及結(jié)果分析結(jié)果分析：輸入的整數(shù)依次為01H，F(xiàn)FH，01H，02H，F(xiàn)FH。結(jié)果輸出：06H。計(jì)算結(jié)果與事實(shí)相符，程序正確執(zhí)行11：進(jìn)行時(shí)序仿真是芯片的引腳分配在進(jìn)行仿真時(shí)主要的引腳分配為：PCARIRCROMR0R1R2R3MUX1MUX2ALUPSWROM262322515161718283023112：故障現(xiàn)象和故障分析1 CMP指令一開始設(shè)為CMP R0，R2導(dǎo)致結(jié)果出錯(cuò)。原來JB指令是小于等于的時(shí)候跳轉(zhuǎn)，所以導(dǎo)致結(jié)果取反。之后將CMP指令改為CMP R2，R0，結(jié)果程序正確。2 微程序控制器中采用全水平微指令，在設(shè)計(jì)AC*DRRd指令時(shí)忘記設(shè)計(jì)S0，S1為1，1，

17、即控制為乘法時(shí)，變成了加法，導(dǎo)致結(jié)果出錯(cuò)。在仿真時(shí)發(fā)現(xiàn)結(jié)果不對(duì)，算的是加法，然后通過修改為乘法，結(jié)果正確。13：軟件清單，含各個(gè)部件的VHDL源程序(.VHD)或圖形描述文件(.gfd)13.1:ALU單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL; -有符號(hào)型ENTITY ALU ISPORT(A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);S1,S0

18、:IN STD_LOGIC;BCDOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);CY,ZI:OUT STD_LOGIC);END ALU;ARCHITECTURE A OF ALU ISSIGNAL AA,BB,TEMP:STD_LOGIC_VECTOR(8 DOWNTO 0);BEGINPROCESS(S1,S0)BEGINIF(S1='0' AND S0='0')THEN -加法AA<='0'&A;BB<='0'&B;TEMP<=AA+BB;BCDOUT<=T

19、EMP(7 DOWNTO 0);CY<=TEMP(8);IF(TEMP="100000000"OR TEMP="000000000")THEN ZI<='1'ELSEZI<='0'END IF;ELSIF(S1='0' AND S0='1')THEN -減法 BCDOUT<=A-B; IF(A<B)THEN CY<='1' ZI<='0'ELSIF(A=B)THEN Y<='0' ZI<=&

20、#39;1'ELSE CY<='0' ZI<='0'END IF; ELSIF(S1='1' AND S0='1')THEN -乘法AA<='0'&A;BB<='0'&B;TEMP<=AA*BB;BCDOUT<=TEMP(7 DOWNTO 0);CY<=TEMP(8);IF(TEMP="100000000"OR TEMP="000000000")THEN ZI<='1'EL

21、SEZI<='0'END IF;ELSIF(S1='1' AND S0='0')THEN -自減1 AA<='0'&A; TEMP<=AA-1;BCDOUT<=TEMP(7 DOWNTO 0);CY<=TEMP(8);IF(TEMP="100000000"OR TEMP="000000000")THEN ZI<='1'ELSEZI<='0'END IF;ELSEBCDOUT<="00000000

22、"CY<='0'ZI<='0'END IF;END PROCESS;END A;13.2: 狀態(tài)條件寄存器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS74 ISPORT(LDFR:IN STD_LOGIC;CY,ZI:IN STD_LOGIC;FC,FZ:OUT STD_LOGIC);END LS74;-狀態(tài)寄存器ARCHITECTURE A OF LS74 ISBEGINPROCESS(LDFR)BEGINIF(LDFR'EVENT AND LDFR='1'

23、;)THEN FC<=CY; FZ<=ZI; END IF;END PROCESS;END A;13.3: 暫存寄存器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS273 ISPORT( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC; O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END LS273;-通用寄存器ARCHITECTURE A OF LS273 ISBEGIN PROCESS(CLK) BEGIN IF(CLK'EVE

24、NT AND CLK='1')THEN O<=D; END IF; END PROCESS;END A;13.4: 3選1數(shù)據(jù)選擇器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX3 ISPORT( ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0); SW_B,CS:IN STD_LOGIC; N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0); EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END MUX3;-3選1數(shù)據(jù)選擇器單元ARCHITE

25、CTURE A OF MUX3 ISBEGIN PROCESS(SW_B,CS) BEGIN IF(SW_B='0')THEN EW<=ID;-從輸入設(shè)備輸入數(shù)據(jù) ELSIF(CS='0')THEN EW<=N2;-將ROM中讀出的指令代碼送入內(nèi)部數(shù)據(jù)通路 ELSE EW<=N1;-將5選1多路選擇器的輸出送入內(nèi)部數(shù)據(jù)通路 END IF; END PROCESS;END A;13.5：5選1數(shù)據(jù)選擇器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX5 ISPORT(C,D,E,F,G: IN

26、 STD_LOGIC;X1,X2,X3,X4,x5: IN STD_LOGIC_VECTOR(7 DOWNTO 0);W: out STD_LOGIC_VECTOR(7 DOWNTO 0);END MUX5;-5選1數(shù)據(jù)選擇器單元ARCHITECTURE A OF MUX5 ISSIGNAL SEL: STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN SEL<=G&F&E&D&C; PROCESS(SEL) BEGIN IF(SEL="11110") THEN -輸出R0的內(nèi)容 W<=X1; ELSIF(SEL

27、="11101") THEN -輸出R1的內(nèi)容 W<=X2; ELSIF(SEL="11011") THEN -輸出R2的內(nèi)容 W<=X3; ELSIF(SEL="10111") THEN -輸出R3的內(nèi)容 W<=X4; ELSIF(SEL="01111") THEN -輸出ALU的內(nèi)容 W<=X5; ELSE null; END IF; END PROCESS;END A;13.6: 程序計(jì)數(shù)器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE I

28、EEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PC ISPORT( LOAD,LDPC,CLR:IN STD_LOGIC; D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END PC;-程序計(jì)數(shù)器ARCHITECTURE A OF PC ISSIGNAL QOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(LDPC,CLR,LOAD) BEGIN IF(CLR='0&

29、#39;)THEN QOUT<="00000000" -將pc清0 ELSIF(LDPC'EVENT AND LDPC='1')THEN IF(LOAD='0')THEN QOUT<=D; -將數(shù)據(jù)總線的內(nèi)容送入pc ELSE QOUT<=QOUT+1; -PC+1 END IF; END IF; END PROCESS; O<=QOUT;END A;13.7: 地址寄存器單元13.8: 主存儲(chǔ)器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LO

30、GIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ROM16 IS PORT(DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CS:IN STD_LOGIC);END ROM16;-主存儲(chǔ)器單元ROM16ARCHITECTURE A OF ROM16 ISBEGINDOUT<="10010001" WHEN ADDR="00000000" AND CS='0' ELSE - M

31、OV R1,00 "00000000" WHEN ADDR="00000001" AND CS='0' ELSE "10010010" WHEN ADDR="00000010" AND CS='0' ELSE -MOV R2,00 "00000000" WHEN ADDR="00000011" AND CS='0' ELSE "10010011" WHEN ADDR="00000100"

32、AND CS='0' ELSE -MOV R3,05 "00000101" WHEN ADDR="00000101" AND CS='0' ELSE "10000000" WHEN ADDR="00000110" AND CS='0' ELSE - L1: IN R0 "11010011" WHEN ADDR="00000111" AND CS='0' ELSE - DEC R3 "10101000&q

33、uot; WHEN ADDR="00001000" AND CS='0' ELSE - CMP R2,R0 "10110000" WHEN ADDR="00001001" AND CS='0' ELSE -JB L2 "00010000" WHEN ADDR="00001010" AND CS='0' ELSE "10101011" WHEN ADDR="00001011" AND CS='0'

34、; ELSE - CMP R2,R3 "10110000" WHEN ADDR="00001100" AND CS='0' ELSE - JB: L1 "00000110" WHEN ADDR="00001101" AND CS='0' ELSE "11100000" WHEN ADDR="00001110" AND CS='0' ELSE - JMP L3 "00010101" WHEN ADDR=&quo

35、t;00001111" AND CS='0' ELSE - "00010000" WHEN ADDR="00010000" AND CS='0' ELSE -L2:MUL R0,R0 "11000001" WHEN ADDR="00010001" AND CS='0' ELSE -ADD R0,R1 "10101011" WHEN ADDR="00010010" AND CS='0' ELSE -CMP

36、 R2,R3 "10110000" WHEN ADDR="00010011" AND CS='0' ELSE -JB L1 "00000110" WHEN ADDR="00010100" AND CS='0' ELSE - "11110100" WHEN ADDR="00010101" AND CS='0' ELSE -L3:OUT1 R1 "00000000"END A;13.9: 指令寄存器單元13.10

37、: 時(shí)序產(chǎn)生器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNTER ISPORT( Q,CLR:IN STD_LOGIC; T2,T3,T4:OUT STD_LOGIC );END COUNTER;-時(shí)序產(chǎn)生器單元ARCHITECTURE A OF COUNTER ISSIGNAL X:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(Q,CLR) BEGIN IF(CLR=&

38、#39;0')THEN T2<='0' T3<='0' T4<='0' X<="00" ELSIF(Q'EVENT AND Q='1')THEN-當(dāng)出現(xiàn)時(shí)鐘Q上邊沿時(shí)，計(jì)數(shù)器的值X+1 X<=X+1;-由當(dāng)前值X譯碼后產(chǎn)生節(jié)拍脈沖信號(hào)T2，T3，T4. T2<=(NOT X(1)AND X(0); T3<=X(1)AND (NOT X(0); T4<=X(1)AND X(0); END IF; END PROCESS;END A;13.11: 微程

39、序控制器單元微程序控制器單元微程序控制器的內(nèi)部結(jié)構(gòu)13.11.1: 地址轉(zhuǎn)移邏輯電路LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDR IS PORT( I7,I6,I5,I4:IN STD_LOGIC; FZ,FC,T4,P1,P2:IN STD_LOGIC; SE6,SE5,SE4,SE3,SE2,SE1:OUT STD_LOGIC);END ADDR;-地址轉(zhuǎn)移邏輯電路ARCHITECTURE A OF ADDR ISBEGIN SE6<='1' SE5<=NOT (NOT FC OR FZ ) AND P

40、2 AND T4); SE4<=NOT(I7 AND P1 AND T4); SE3<=NOT(I6 AND P1 AND T4); SE2<=NOT(I5 AND P1 AND T4); SE1<=NOT(I4 AND P1 AND T4);END A;13.11.2: 微地址寄存器微地址寄存器內(nèi)部結(jié)構(gòu)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MMM ISPORT( SE:IN STD_LOGIC; T2:IN STD_LOGIC; D:IN STD_LOGIC; CLR:IN STD_LOGIC; UA:OUT

41、STD_LOGIC);END MMM;-帶有異步清零和異步置一功能的觸發(fā)器，由多個(gè)mmm組成微地址寄存器aaARCHITECTURE A OF MMM ISBEGIN PROCESS(CLR,SE,T2) BEGIN IF(CLR='0')THEN UA<='0' ELSIF(SE='0')THEN UA<='1' ELSIF(T2'EVENT AND T2='1')THEN UA<=D; END IF; END PROCESS;END A;13.11.3: 微地址轉(zhuǎn)換器LIBRARY I

42、EEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F1 ISPORT( UA5,UA4,UA3,UA2,UA1,UA0:IN STD_LOGIC; D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0) );END F1;-微地址轉(zhuǎn)換器ARCHITECTURE A OF F1 ISBEGIN D(5)<=UA5; D(4)<=UA4; D(3)<=UA3; D(2)<=UA2; D(1)<=UA1; D(0)<=UA0;END A;13.11.4: 控制存儲(chǔ)器LIBRARY IEEE;USE IEEE.STD_LOG

43、IC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CONTROM ISPORT(ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); D:OUT STD_LOGIC_VECTOR(18 DOWNTO 0) );END CONTROM;-操作控制器單元ARCHITECTURE A OF CONTROM ISSIGNAL DATAOUT: STD_LOGIC_VECTOR(24 DOWNTO

44、0);BEGIN PROCESS(ADDR) BEGIN CASE ADDR IS WHEN "000000" => DATAOUT<="1110011001001111000000010" WHEN "000010" => DATAOUT<="1001011001001011010000000"-取指 WHEN "000001" => DATAOUT<="1000010001101111000010101" WHEN "0101

45、01" => DATAOUT<="1000001001011111000010110" WHEN "010110" => DATAOUT<="1000111110001111000000000"-MUL WHEN "001000" => DATAOUT<="1000111001001101000000000"-IN WHEN "001001" => DATAOUT<="11100110010011110000

46、00011" WHEN "000011" => DATAOUT<="1000111001001011000000000"-MOV WHEN "001010" => DATAOUT<="1000010001101111000000100" WHEN "000100" => DATAOUT<="1000001001011111000000101" WHEN "000101" => DATAOUT<=&q

47、uot;1000011011001111100000000"-CMP WHEN "001011" => DATAOUT<="1110011001001111001100000" WHEN "100000" => DATAOUT<="0100011001001011000000000" WHEN "110000" => DATAOUT<="1000011001001111000000000" -JB WHEN "00110

48、0" => DATAOUT<="1000010001101111000000110" WHEN "000110" => DATAOUT<="1000001001011111000000111" WHEN "000111" => DATAOUT<="1000111000001111000000000"-ADD WHEN "001101" => DATAOUT<="100000100110111100001001

49、0" WHEN "010010" => DATAOUT<="1000111100001111000000000"-INC WHEN "001110" => DATAOUT<="1110011001001111000010011" WHEN "010011" => DATAOUT<="0100011001001011000000000"-JMP WHEN "001111" => DATAOUT<=&q

50、uot;1000010001000110000000000"-OUT WHEN OTHERS => DATAOUT<="1110011001001111000000010" END CASE; UA(5 DOWNTO 0)<=DATAOUT(5 DOWNTO 0); D(18 DOWNTO 0)<=DATAOUT(24 DOWNTO 6); END PROCESS;END A;13.11.5: 微指令寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MCOMMAND ISPORT( T2,T3,T4,I3,I2,I1,I0:IN STD_LOGIC; O