EDA考試題目和答案

1、設(shè)計實驗與考核1、設(shè)計一個帶計數(shù)使能、異步復(fù)位、帶進(jìn)位輸出的增1 六位二進(jìn)制計數(shù)器，計數(shù)結(jié)果由共陰極七段數(shù)碼管顯示。答： library ieee;useuseentity counter isport(clk,clk1,en,clr:in std_logic;ledout:out std_logic_vector(6 downto 0); scanout,scanout1,co:out std_logic);end counter;architecture a of counter issignal cnt:std_logic_vector(7 downto 0);signal led:st

2、d_logic_vector(6 downto 0);signal scan:std_logic;signal hex:std_logic_vector(3 downto 0);beginprocess(clk)beginif(clk'event and clk='1')thenif en='1'thenif clr='1'thencnt<=(others=>'0');elseif cnt="00111111"thencnt<="00000000"co<=&#

3、39;1'elsecnt<=cnt+'1'co<='0'end if;end if;end if;end if;end process;process(clk1)beginif clk1'event and clk1='1'then scan<=not scan;end if;Scanout=scan;Scanout1=not scan;end process;ledout<=not led;hex<=cnt(7 downto 4) when scan='1'else cnt(3 do

4、wnto 0);with hex select led<="1111001"when"0001","0100100"when"0010","0110000"when"0011","0011001"when"0100","0010010"when"0101","0000010"when"0110","1111000"when"

5、;0111","0000000"when"1000","0010000"when"1001","0001000"when"1010","0000011"when"1011","1000110"when"1100","0100001"when"1101","0000110"when"1110","00

6、01110"when"1111", "1000000"when others;end a;2、設(shè)計一個帶計數(shù)使能、同步復(fù)位、帶進(jìn)位輸出的增1 二十進(jìn)制計數(shù)器，計數(shù)結(jié)果由共陰極七段數(shù)碼管顯示。答： library ieee;useuse counter isport(clk,clk1,en,clr:in std_logic; co,scanout:out std_logic; ledout:out std_logic_vector(6 downto 0);end counter; architecture rtl of counter is si

7、gnal cnt:std_logic_vector(7 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic; signal hex:std_logic_vector(3 downto 0);beginprocess(clk,clr)beginif clr='1'thencnt<=(others=>'0');elsif clk'event and clk='1' thenif en='1'thenif cnt=&quo

8、t;00001001"then cnt<="00010000" co<='0'elsif cnt="00011001"then - 注意此處，前面跳過了 A 到 F 的計數(shù) ,所以計數(shù)到 11001 cnt<="00000000"co<='1'elsecnt<=cnt+'1' co<='0'end if;end if;end if;end process;process(clk1)beginif clk1'event

9、and clk1='1'then scan<=not scan;end if;end process;ledout<=not led;scanout<=scan;hex<=cnt(7 downto 4) when scan='1'else cnt(3 downto 0);with hex selectled<="1111001"when"0001","0100100"when"0010","0110000"when"0011

10、","0011001"when"0100","0010010"when"0101","0000010"when"0110","1111000"when"0111","0000000"when"1000","0010000"when"1001","1000000"when"0000","1111111

11、"when others;end rtl;3、設(shè)計一個帶計數(shù)使能、異步復(fù)位、同步裝載的可逆七位二進(jìn)制計數(shù)器，計數(shù)結(jié)果由共陰 極七段數(shù)碼管顯示。答： library ieee;useuseentity counter isport(clk,clks,clr,en,stdl,dir:in std_logic;din:in std_logic_vector(6 downto 0);ledout:out std_logic_vector(6 downto 0);scanout:out std_logic);end counter;architecture a of counter issig

12、nal cnt:std_logic_vector(6 downto 0);signal hex:std_logic_vector(3 downto 0);signal led:std_logic_vector(6 downto 0);signal scan:std_logic;beginprocess(clk)beginif(clk'event and clk='1')thenif clr='1'thencnt<=(others=>'0');elsif stdl='0'thencnt<=din;elsif

13、 en='1'thenif dir='1'thencnt<=cnt+'1'elsecnt<=cnt-'1'end if;end if;end if;end process;process(clks)beginif(clks'event and clks='1')thenscan<=not scan;end if;end process;scanout<=scan;ledout<=not led;hex<='0'&cnt(6 downto 4)whe

14、n scan='1' else cnt(3 downto 0);with hex selectled<="1111001"when"0001","0100100"when"0010","0110000"when"0011","0011001"when"0100","0010010"when"0101","0000010"when"0110&quo

15、t;,"1111000"when"0111","0000000"when"1000","0010000"when"1001","0001000"when"1010","0000011"when"1011","1000110"when"1100","0100001"when"1101", "0000110&qu

16、ot;when"1110","0001110"when"1111", "1000000"when others;end a;4、設(shè)計一個帶計數(shù)使能、同步復(fù)位、異步裝載、可逆計數(shù)的通用計數(shù)器。計數(shù)結(jié)果由共陰 極七段數(shù)碼管顯示。答： LIBRARY IEEE;USEUSE counter ISGENERIC (count_value:INTEGER:=9);PORT(clk,clr,en,load,dir:IN STD_LOGIC;data_in:IN INTEGER RANGE 0 TO count_value;le

17、dout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END counter;ARCHITECTURE a OF counter ISSIGNAL cnt:INTEGER RANGE 0 TO count_value;SIGNAL led:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGINPROCESS(load,clk)BEGINIF load='1' THENcnt<=data_in;elsif clr='1' THENcnt<=0;ELSIF (clk'EVENT AND clk='1&#

18、39;)THENIF en='1' THENIF dir='1' THENIF cnt=count_value THENcnt<=0;ELSEcnt<=cnt+1;end if;elseIF cnt=0 THENcnt<=count_value;elsecnt<=cnt-1;end if;end if;end if;end if;END PROCESS; ledout<=NOT led;WITH cnt SELECT led<="1111001"WHEN 1,"0100100"WHEN

19、2,"0110000"WHEN 3,"0011001"WHEN 4,"0010010"WHEN 5,"0000010"WHEN 6,"1111000"WHEN 7,"0000000"WHEN 8,"0010000"WHEN 9,"1000000"WHEN 0,"1111111"WHEN others;END a;5、設(shè)計一個具有 16 分頻、8 分頻、4 分頻和 2分頻功能的多用分頻器答： LIBRARY IEEE;

20、USEUSEENTITY div4 ISPORT(clk:IN STD_LOGIC;din:IN STD_LOGIC_VECTOR(3 DOWNTO 0); fout:OUT std_LOGIC);END div4;ARCHITECTURE a OF div4 ISbeginprocess(clk)variable cnt:std_logic_vector(3 downto 0);beginif(clk'event and clk='1') thenif cnt="1111" thencnt:="0000"elsecnt:=cnt

21、+'1'end if;if din="0000" thenfout<=cnt(3);elsif din="1000" thenfout<=cnt(2);elsif din="1100" thenfout<=cnt(1);elsif din="1110" thenfout<=cnt(0);elsefout<='1'end if;end if;end process;end a;6、設(shè)計一個正負(fù)脈寬相等的通用分頻器。答： LIBRARY IEEE;USEUS

22、EENTITY div ISGENERIC (num:INTEGER:=2);PORT(clk:IN STD_LOGIC;co:OUT STD_LOGIC);END div;ARCHITECTURE rtl OF div ISBEGINPROCESS(clk)VARIABLE cnt:STD_LOGIC_VECTOR(num downto 0);BEGINIF(clk'event and clk='1')THENcnt:=cnt+'1'END IF;co<=cnt(num);END PROCESS;END rtl;7、根據(jù)需要設(shè)計一個多用分頻器：可

23、以控制實現(xiàn)四種分頻形式： 第一種： 5 分頻 第二種： 8 分頻 第三種： 15 分頻 第四種： 16 分頻答： library ieee;useuseentity fenpin is port(clk:in std_logic;en:in std_logic_vector(1 downto 0);cout:out std_logic;ledout:out std_logic_vector(6 downto 0);end fenpin;architecture dgnfenpin of fenpin issignal led:std_logic_vector(6 downto 0);signa

24、l hex:std_logic_vector(3 downto 0);beginprocess(clk)variable cnt:std_logic_vector(3 downto 0)= ”0000”; beginif(clk'event AND clk='1')then if(en="00")thenif(cnt>="0101")then cnt:="0000"elsecnt:=cnt+'1'end if;cout<=cnt(2);elsif(en="01")

25、then if(cnt>="1000")thencnt:="0000"cout<='1'elsecnt:=cnt+'1' cout<='0'end if;elsif(en="10")then if(cnt>="1110")then cnt:="0000"cout<='1'elsecnt:=cnt+'1'cout<='0'end if;elseif(cnt>=&

26、quot;1111")thencnt:="0000"elsecnt:=cnt+'1'end if;cout<=cnt(3);end if;end if;end process;with en selectled<="0000000"when"00","0001000"when"01","0001110"when"10","1000000"when"11","111111

27、1"when others;ledout<=led;end dgnfenpin;8、設(shè)計一個 M 序列發(fā)生器， M 序列為library ieee;useuseentity xulie isport(clk:in std_logic;fout:out std_logic);end xulie;architecture fashengqi of xulie issignal cnt:std_logic_vector(2 downto 0);beginprocess(clk)beginif(clk'event AND clk='1')thenif(cnt=&

28、quot;111")thencnt<="000"elsecnt<=cnt+'1'end if;end if;end process;with cnt selectfout<='1'when"000",'1'when"001",'1'when"010",'1'when"011",'0'when"100",'1'when"101&q

29、uot;,0'when “110”,1'when ”111”,0'when others;end fashengqi;9、設(shè)計一個彩燈控制器，彩燈共有 16 個，每次順序點亮相鄰的四個彩燈，如此循環(huán)執(zhí)行， 循環(huán)的方向可以控制。答： library ieee;useentity caideng isport( rl,clk:in std_logic;ledout:out std_logic_vector(15 downto 0);end caideng;architecture a of caideng issignal led:std_logic_vector(15 d

30、ownto 0);signal k:std_logic;beginprocess(clk)beginif(clk'event and clk='1')thenif(k='0')thenled<=(0=>'1',1=>'1',2=>'1',3=>'1',others=>'0');elsif(rl='1')thenled<=led(14 downto 0)&led(15);elsif(rl='0')

31、thenled<=led(0)&led(15 downto 1);end if;end if;ledout<=led;end process;8 位串行移位寄存器end a;10、設(shè)計一個具有左移、右移控制，同步并行裝載和串行裝載的LIBRARY IEEE;USE shifter1 ISPORT(clk,clr,ser,dir,stld:IN STD_LOGIC;din: IN STD_LOGIC_VECTOR(0 TO 7) ;qh:OUT STD_LOGIC);END shifter1;ARCHITECTURE rt1 OF shifter1 ISSIGNAL reg:

32、STD_LOGIC_VECTOR(0 TO 7);beginprocess(clk,clr)beginif clr='1' thenreg<=(others=>'0');elsif clk'event and clk='1'thenif stld='0'thenreg<=din;elseif(dir='0')thenreg<=reg(1 to 7)&ser;qh<=reg(0);elsereg<=ser&reg(0 to 6);qh<=reg(7);

33、end if;end if;end if;end process;end rt1;11、設(shè)計一個 9 人表決電路，參加表決者為 9 人，同意為 1，不同意為 0，同意者過半則表 決通過，綠指示燈亮，表決不通過則紅指示燈亮。數(shù)碼管顯示贊成人數(shù)。library ieee;useuseentity selector isport(a:in std_logic_vector(8 downto 0);clr:in std_logic;red,gree:out std_logic;ledout:out std_logic_vector(6 downto 0);end selector;architectu

34、re rtl of selector issignal led:std_logic_vector(6 downto 0);signal count:std_logic_vector(3 downto 0);beginprocess(a)variable cnt:std_logic_vector(3 downto 0);begincnt:= ”0000”;for i in 0 to 8 loopif a(i)= '1' thencnt:=cnt+1;end if;end loop;if(cnt>= ”0101 ”and cnt<= ”1001 ”)thengree&l

35、t;='1'red<= '0'elsif(cnt>= ”0000 ”and cnt<= ”0100”)thengree<='0'red<= '1'end if;count<=cnt;end process;ledout<=not led;with count select led<="1111001"when"0001","0100100"when"0010","0110000"whe

36、n"0011","0011001"when"0100","0010010"when"0101","0000010"when"0110",“1111000”when ”0111”,“0000000”when ”1000”,“0010000”when ”1001”, "1000000"when others;end rtl;12、設(shè)計一個同步復(fù)位，異步并行裝載的 8 位串行左移移位寄存器LIBRARY IEEE;USE exam13 isP

37、ort(clk,clr,ser,stld:in std_logic;Din:in std_logic_vector(0 to 7);Qh:out std_logic);End exam13;Architecture rtl of exam13 isSignal reg:std_logic_vector(0 to 7);BeginProcess(clk,stld)BeginIf stld= '1' thenReg<=din;Elsif clk'event and clk='1' thenIf clr='1' thenReg<=(

38、others>='0');Elsif(stld='0')thenReg<=reg(1 to 7)&ser;End if;End if;End process;Qh<=reg(0);End rtl;1 時由共陰13、有 16 個開關(guān)，編號為 0 到 15，編號 0 的優(yōu)先級最高。當(dāng)某一個撥碼開關(guān)為 極七段數(shù)碼管顯示其編號(可用 16 進(jìn)制數(shù)顯示，亦可用十進(jìn)制顯示)答： LIBRARY IEEE;USEUSE bhxs ISPORT(INPUT:IN STD_LOGIC_VECTOR(15 DOWNTO 0);LEDOUT: out STD

39、_LOGIC_VECTOR(6 DOWNTO 0);END bhxs;ARCHITECTURE RT1 OF bhxs ISSIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN process(INPUT) beginLEDOUT<=NOT LED;IF(INPUT(0)='1')then LED<="1000000"ELSIF(INPUT(1)='1')then LED<="1111001"ELSIF(INPUT(2)='1')then LED<

40、;="0100100"ELSIF(INPUT(3)='1')then LED<="0110000"ELSIF(INPUT(4)='1')then LED<="0011001"ELSIF(INPUT(5)='1')then LED<="0010010"ELSIF(INPUT(6)='1')thenLED<="0000010"ELSIF(INPUT(7)='1')thenLED<="

41、;1111000"ELSIF(INPUT(8)='1')thenLED<="0000000"ELSIF(INPUT(9)='1')thenLED<="0010000"ELSIF(INPUT(10)='1')thenLED<="0001000"ELSIF(INPUT(11)='1')thenLED<="0000011"ELSIF(INPUT(12)='1')thenLED<="100011

42、0"ELSIF(INPUT(13)='1')thenLED<="0100001"ELSIF(INPUT(14)='1')thenLED<="0000110"ELSIF(INPUT(15)='1')thenLED<="0001110"END IF;END PROCESS;END RT1;14、設(shè)計一個全自動洗衣機(jī)水位控制器。要求：當(dāng)水位超過某一上限值時，停止加水，啟動洗衣機(jī)；當(dāng)水位低于某一下限值時，加 水，停止洗衣機(jī)；否則啟動洗衣機(jī)，停止加水。LIBRARY I

43、EEE;USE washer isPort(clk,water_high,water_low:in std_logic;Jiashui,qidong:out std_logic);End washer;Architecture style of washer isType state is(just_right,too_high,too_low);Signal now_state,next_state:state;BeginProcess(now_state,water_high,water_low)BeginCase now_state isWhen just_right=>jiash

44、ui<= ' ;0q'idong<= '1'If water_low= '1'then next_state<=too_low;Elsif water_high= '1'then next_state<=too_high;Else next_state<=just_right;End if;When too_low=>jiashui<= '1'qidong<= '0'If water_low= '1'then next_state<

45、;=too_low;Elsif water_high= '1'then next_state<=too_high;Else next_state<=just_right;End if;When too_high=>jiashui<= '0'qidong<= '1'If water_low= '1'then next_state<=too_low;Elsif water_high= '1'then next_state<=too_high;Else next_state<

46、;=just_right;End if;End case,End process;Process(clk)BeginIf(clk 'event and clk= '1')then Now_state<=next_state;End if;End process;8位加法器End style;15、根據(jù)真值表設(shè)計一位全加器，然后用結(jié)構(gòu)的描述方法設(shè)計一個LIBRARY IEEE;USEENTITY full_adder ISPORT(a,b,cin:IN STD_LOGIC;s,co:OUT STD_LOGIC);END full_adder;ARCHITECTURE

47、 full1 of full_adder isSIGNAL comb:STD_LOGIC_VECTOR(2 downto 0);BEGINcomb<=a&b&cin;PROCESS(comb)BEGINIF(comb="000")thens<='0'co<='0'elsif(comb="001")then s<='1'co<='0'elsif(comb="100")then s<='1'co<=&#

48、39;0'elsif(comb="010")thens<='1'co<='0'elsif(comb="011")then s<='0'co<='1'elsif(comb="101")then s<='0'co<='1'elsif(comb="110")then s<='0'co<='1'elses<='1'co&

49、lt;='1'end if;end process;end full1;library ieee;useentity full_adder8 isport(clk,cin:in std_logic;x,y:in std_logic_vector(7 downto 0); ledout:out std_logic_vector(6 downto 0); scan_out:out std_logic_vector(1 downto o); co:out std_logic);end full_adder8;architecture stru of full_adder8 is co

50、mponent full_adderport(a,b,cin:in std_logic;s,co:out std_logic);end component;signal z:std_logic_vector(6 downto 0);signal sum:std_logic_vector(7 downto 0);signal scan:std_logic_vector(1 downto 0);signal hex:std_logic_vector(3 downto 0);signal led:std_logic_vector(6 downto 0);beginuo:full_adder port

51、 map(x(0),y(0),cin,sum(0),z(0);u1:full_adder port map(x(1),y(1),z(0),sum(1),z(1);u2:full_adder port map(x(2),y(2),z(1),sum(2),z(2);u3:full_adder port map(x(3),y(3),z(2),sum(3),z(3);u4:full_adder port map(x(4),y(4),z(3),sum(4),z(4);u5:full_adder port map(x(5),y(5),z(4),sum(5),z(5);u6:full_adder port

52、map(x(6),y(6),z(5),sum(6),z(6); u7:full_adder port map(x(7),y(7),z(6),sum(7),co); scan_out<=scan;ledout<=not led;process(clk)beginif(clk 'event and clk= '1')thenif scan=”10” thenscan<=”01”;else scan<=”10”;end if;end if;end process;hex<=sum(7 downto 4)when scan= ”10” elsesu

53、m(3 downto 0);with hex select led<=”1000000”when ”0000”,“1111001”when ”0001”,“0100100”when ”0010”,“0110000”when ”0011”,“0011001”when ”0100”,“0010010”when ”0101”,“0000010”when ”0110”,“1111000”when ”0111”,“0000000”when ”1000”,“0010000”when ”1001”,“0001000”when ”1010”,“0000011”when ”1011”,“1000110”w

54、hen ”1100”,“0100001”when ”1101”,“0001110”when ”1110”,“0001110”when ”1111”,“XXXXXXX” when others;End stru;16、設(shè)計 6 位二進(jìn)制數(shù)到 BCD碼( 8421碼)的轉(zhuǎn)換器。結(jié)果由共陰極數(shù)碼管顯示LIBRARY IEEE;USEuse trans ISPORT(scanclk:IN STD_LOGIC;shu:IN STD_LOGIC_VECTOR(5 DOWNTO 0);ledout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); scanout:out integer r

55、ange 0 to 1);END trans;ARCHITECTURE rtl OF trans ISsignal yh,yl:integer range 0 to 9;signal scan:integer range 0 to 1;signal led:std_logic_vector(6 downto 0);signal y,hex:integer range 0 to 63;BEGINy<=conv_integer(shu);yh<=1 when y>=10 and y<20 else2 when y>=20 and y<30 else3 when

56、y>=30 and y<40 else4 when y>=40 and y<50 else5 when y>=50 and y<60 else6 when y>=60 and y<64 else0;yl<=(y-0) when y>=0 and y<10 else (y-10)when y>=10 and y<20 else (y-20)when y>=20 and y<30 else (y-30)when y>=30 and y<40 else (y-40)when y>=40 and

57、 y<50 else (y-50)when y>=50 and y<60 else (y-60)when y>=60 and y<70 else 0;process(scanclk)beginif(scanclk'event and scanclk='1')then if scan=1 thenscan<=0;elsescan<=1;end if;end if;end process;with scan selecthex<=yh when 1,yl when others;ledout<=not led; scan

58、out<=scan;with hex select led<="1111001"when 1, "0100100"when 2, "0110000"when 3, "0011001"when 4, "0010010"when 5, "0000010"when 6, "1111000"when 7, "0000000"when 8, "0010000"when 9, "1000000"w

59、hen 0,“1111001 ”when others;END rtl;17、設(shè)計一個跑馬燈控制器。一共有 8 個彩燈，編號為 LED0LED，7 點亮方式為：先從左往 右順序點亮，然后從右往左，如此循環(huán)往復(fù)。答： LIBRARY IEEE;USEUSEENTITY lighten ISPORT(CLK:IN STD_LOGIC;ledout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END lighten;ARCHITECTURE b OF lighten ISSIGNAL cnt:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(C

60、LK)BEGINIF(CLK'EVENT AND CLK='1')THENIF (cnt="1110")THEN cnt<="0000"ELSEcnt<=cnt+'1'END IF;END IF;END PROCESS;WITH cnt SELECTledout<= ""WHEN"0000","01000000"WHEN"0001","00100000"WHEN"0010",&q

61、uot;00010000"WHEN"0011","00001000"WHEN"0100","00000100"WHEN"0101","00000010"WHEN"0110","00000001"WHEN"0111","00000010"WHEN"1000","00000100"WHEN"1001","00001000&

62、quot;WHEN"1010","00010000"WHEN"1011","00100000"WHEN"1100","01000000"WHEN"1101",""WHEN"1110","00000000"WHEN OTHERS;END b;10位的LIBRARY IEEE;USEUSEENTITY lighten ISPORT(CLK:IN STD_LOGIC;ledout:OUT STD_LOG

63、IC_VECTOR(9 DOWNTO 0);END lighten;ARCHITECTURE b OF lighten ISSIGNAL cnt:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENT AND CLK='1')THENIF (cnt="10010")THENcnt<="00000"ELSEcnt<=cnt+'1'END IF;END IF;END PROCESS;WITH cnt SELECTledout<=

64、"00"WHEN"00000","00"WHEN"00001","00"WHEN"00010","0001000000"WHEN"00011","0000100000"WHEN"00100","0000010000"WHEN"00101","0000001000"WHEN"00110","0000000100

65、"WHEN"00111","0000000010"WHEN"01000","0000000001"WHEN"01001","0000000010"WHEN"01010","0000000100"WHEN"01011","0000001000"WHEN"01100","0000010000"WHEN"01101","00

66、00100000"WHEN"01110","0001000000"WHEN"01111","00"WHEN"10000","00"WHEN"10001","00"WHEN"10010","0000000000"WHEN OTHERS;END b;18、有四路數(shù)據(jù)輸入，每路數(shù)據(jù)為 4 位二進(jìn)制數(shù)，根據(jù)不同的控制信號，輸出相應(yīng)的輸入數(shù) 據(jù)。同時由共陰極七段數(shù)碼管顯示輸出數(shù)據(jù)的路號。libra

67、ry ieee;useentity exam27 isport(a:in std_logic_vector(3 downto 0);b:out std_logic_vector(6 downto 0);end exam27;architecture rtl of exam27 issignal e:std_logic_vector(6 downto 0);signal c,d:integer range 0 to 9;beginc<=conv_integer(a);d<=10-c;with d selecte<="1111001"when 1,"

68、0100100"when 2,"0110000"when 3,"0011001"when 4,"0010010"when 5,"0000010"when 6,"1111000"when 7,"0000000"when 8,“0010000”when 9, "1000000"when others;b<=not e;end rtl;19、設(shè)計五位 BCD碼(8421 碼)到十六進(jìn)制數(shù)的轉(zhuǎn)換器。結(jié)果由共陰極數(shù)碼管顯示答： library iee

69、e;useuseentity bcd2hex isport(shu:in std_logic_vector(4 downto 0);scanclk:in std_logic;led_out:out std_logic_vector(6 downto 0);scan_out:out integer range 0 to 1);end bcd2hex;architecture rt1 of bcd2hex issignal yh,yl :integer range 0 to 15;signal scan:integer range 0 to 1;signal led:std_logic_vector(6 downto 0);signal y,hex:integer range 0 to 31;beginy<=conv_integer(shu);yh<=1 when y>=16 and y<32