基于Verilog的數(shù)字密碼鎖設(shè)計(jì)

1、課程設(shè)計(jì)報(bào)告課程設(shè)計(jì)題目：基于Verilog的數(shù)字密碼鎖設(shè)計(jì) 學(xué) 號(hào)：201520070209學(xué)生姓名：尹景興專 業(yè)：通信工程班 級(jí)：1521301指導(dǎo)教師：鐘凱 2018年 1月 12 日目 錄一、課程設(shè)計(jì)內(nèi)容- 1 -二、實(shí)現(xiàn)思路- 1 -1.解鎖過程- 1 -2.報(bào)警過程- 1 -3.重置密碼過程- 1 -三、實(shí)現(xiàn)程序- 2 -四、仿真驗(yàn)證- 5 -1.解鎖過程- 5 -2.報(bào)警過程- 6 -3.重置密碼過程- 8 -五、設(shè)計(jì)心得- 11 -一、 課程設(shè)計(jì)內(nèi)容設(shè)計(jì)一個(gè)4位串行數(shù)字密碼鎖，要求如下：1. 開鎖密碼為4位二進(jìn)制，當(dāng)輸入密碼與鎖內(nèi)給定的密碼一致時(shí)，方可開鎖。否則進(jìn)入“錯(cuò)誤”狀態(tài)

2、，發(fā)出報(bào)警信號(hào)。2. 鎖內(nèi)的密碼可調(diào)。3. 串行數(shù)字密碼鎖的報(bào)警，直到按下復(fù)位開關(guān)，才停下。此時(shí)，數(shù)字密碼鎖又自動(dòng)等待下一個(gè)開鎖狀態(tài)。二、 實(shí)現(xiàn)思路1. 解鎖過程密碼鎖出廠之前預(yù)設(shè)一個(gè)初始密碼，在本課程設(shè)計(jì)中將其預(yù)設(shè)為0101。在密碼鎖上鎖狀態(tài)下,輸入正確密碼，密碼鎖打開。2. 報(bào)警過程當(dāng)輸入的密碼與鎖內(nèi)密碼不一致時(shí)，蜂鳴器響起，直到按下取消按鍵，蜂鳴器才停止鳴叫。3. 重置密碼過程重置密碼時(shí)，需先驗(yàn)證原密碼是否正確。當(dāng)輸入原密碼正確，才可以輸入新密碼，設(shè)置新密碼為鎖內(nèi)密碼。三、 實(shí)現(xiàn)程序module coded_lock(clk,in,set,pause,value1,value2,stor

3、e,bee,status,temp_set,ook); input clk,in,set,pause; output reg bee = 0; output reg status = 0; output reg temp_set = 0; output reg ook = 0; output reg3:0 value1; output reg3:0 value2; output reg3:0 store; reg en = 1; reg2:0 i = 0; reg2:0 j = 0; reg2:0 k = 0; reg2:0 count1 = 0; reg2:0 count2 = 0; reg

4、2:0 count3 = 0; reg3:0 keynum = 4'b0101; always (posedge clk) begin if(set = 1) fork temp_set <= 1; value1 <= 4'bxxxx; value2 <= 4'bxxxx; store <= 4'bxxxx; i <= 0; j <= 0; k <= 0; ook <= 0; count1 <= 0; count2 <= 0; count3 <= 0; join end always (posed

5、ge clk) begin if(temp_set = 0) begin case(en,in) 2'b11: begin value1i <= 1'b1; i <= i + 1; count1 <= count1 + 1;end 2'b10: begin value1i <= 1'b0; i <= i + 1; count1 <= count1 + 1;end endcase end end always (posedge clk) begin if(count1 = 4) begin if(value1 = keynum)

6、 status <= 1; else bee <= 1; i <= 0; count1 <= 0; value1 <= 4'bxxxx; end end always (posedge clk) begin if(pause = 1) bee <= 0; end always (posedge clk) begin if(temp_set = 1 && ook = 0) begin case(en,in) 2'b11: begin value2j <= 1'b1; j <= j + 1; count2 &l

7、t;= count2 + 1;end 2'b10: begin value2j <= 1'b0; j <= j + 1; count2 <= count2 + 1;end endcase end end always (posedge clk) begin if(count2 = 4) begin if(value2 = keynum) ook <= 1; j <= 0; count2 <= 0; value2 <= 4'bxxxx; end end always (posedge clk) begin if(ook = 1)

8、begin case(en,in) 2'b11: begin storek <= 1'b1; k <= k + 1; count3 <= count3 + 1;end 2'b10: begin storek <= 1'b0; k <= k + 1; count3 <= count3 + 1;end endcase end end always (posedge clk) begin if(count3 = 4) begin keynum <= store; temp_set <= 0; ook <= 0; k

9、 <= 0; count3 <= 0; end end endmodule 四、 仿真驗(yàn)證1. 解鎖過程測(cè)試平臺(tái)代碼：timescale 1ns/1nsmodule text; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(status),.value1(va

10、lue1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1'bx; set = 0; pause = 0; join initial begin #123 in = 1'b1; #23 in = 1'bx; #45 in = 1'b0; #23 in = 1'bx; #45 in = 1'b1; #23 in = 1'bx; #45 in = 1'b0; #23 in = 1&

11、#39;bx; end endmodule 如圖，當(dāng)輸入預(yù)設(shè)密碼0101時(shí)，圖中status由0變?yōu)?，表示密碼鎖打開。2. 報(bào)警過程測(cè)試平臺(tái)代碼：timescale 1ns/1nsmodule text3; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp3(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(status)

12、,.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1'bx; set = 0; pause = 0; join initial begin #123 in = 1'b1; #23 in = 1'bx; #45 in = 1'b1; #23 in = 1'bx; #45 in = 1'b0; #23 in = 1'bx; #45 in = 1'b0;

13、#23 in = 1'bx; #123 pause = 1; #23 pause = 0; end endmodule如下圖，當(dāng)輸入密碼0011時(shí)，與鎖內(nèi)密碼不一致，bee由0變?yōu)?，表示蜂鳴器響起。當(dāng)按下pause按鈕時(shí)，bee由1變?yōu)?，表示蜂鳴器停止鳴叫。3. 重置密碼過程測(cè)試平臺(tái)代碼：timescale 1ns/1nsmodule text2; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp2(

14、.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(status),.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1'bx; set = 0; pause = 0; join initial begin #123 set = 1; #21 set = 0; #123 in = 1'b1; #21 in = 1

15、'bx; #45 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #45 in = 1'b0; #21 in = 1'bx; #125 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #45 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #125 in = 1'b0; #21

16、in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #45 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx;end endmodule 如下圖，當(dāng)正確輸入預(yù)設(shè)密碼0101時(shí)，ook由0變?yōu)?，表示可以更改密碼，更改密碼為1010。接著，輸入新密碼1010，status由0變?yōu)?，表示密碼鎖被新密碼打開，如下圖。五、 設(shè)計(jì)心得通過這次課程設(shè)計(jì)，我更深入熟悉了Verilog編程的各個(gè)過程和原理，并且，成功地做出了一個(gè)產(chǎn)品的簡(jiǎn)化模型極大地挺高了我的學(xué)習(xí)興趣。當(dāng)然，設(shè)計(jì)過程中也遇到了各種問題和困難，我極力克服，過后感覺受益匪淺。我會(huì)再接再厲的。Bingo!- 11 -東華理工大學(xué)課程設(shè)計(jì)評(píng)分表學(xué)生姓名：尹景興 班級(jí)：1521301 學(xué)號(hào)：201520070209課程設(shè)計(jì)題目：基于Verilog的數(shù)字密碼鎖設(shè)計(jì) 項(xiàng)目?jī)?nèi)容滿分實(shí) 評(píng)選題能結(jié)合所學(xué)課程知識(shí)、有一定的能力訓(xùn)練。符合選題要求（5人一題）10工作量適中，難易度合理10能力水平能熟練應(yīng)用所學(xué)知識(shí)，有一定查閱文