無傳感器的BLDC電機(jī)控制

1、 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng) A Variable-Speed Sensorless System for BLDC Motor Sunplus Technology Co., Ltd. PAGE 1 V1.1 Dec 8, 2005 Important NoticeSUNPLUS TECHNOLOGY CO. reserves the right to change this documentationwithout prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate a

2、nd reliable. However, SUNPLUS TECHNOLOGY CO. makes nowarranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement

3、of patentor other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support systems or aviation systems, where a malfunction or failure of the product may reasonably be expected to result in significant inju

4、ry to the user, without the express written approval of Sunplus. 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 A Variable-Speed Sensorless System for BLDC Motor Sunplus Technology Co., Ltd. PAGE 2 V1.1 Dec 8, 2005 Table of Content1SPMC75F2413A BLDC controller.1 1.1Introduction. 11.2SUNPLUS SPMC75F2413A Controller Feature

5、s. 12Position SensorlessControl of BLDCMotor. 5 2.1BLDC Motorand PWM.5 2.2Position SensorlessControl. 7 2.3Alignment for Absolute Position. 9 2.4Position SensorlessControl Flow.92.5Sensorless BLDC Drive System Implementation.103Experimental Results. 12 4Application Example Code.14 5Reference. 22 專業(yè)單

6、片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 A Variable-Speed Sensorless System for BLDC Motor Sunplus Technology Co., Ltd. PAGE 3 V1.1 Dec 8, 2005 Revision HistoryRevision Date By RemarkPage Number(s V 1.1 2005/12/8UpdateV1.02004/10/26First 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 A Variable-Speed Sensorless System for BLDC Motor Sunplus

7、Technology Co., Ltd. PAGE 1 V1.1 Dec 8, 2005 1SPMC75F2413A BLDC controller1.1 IntroductionThe SPMC75F2413A digitalmotor controller developedby SUNPLUS is well suitable forwide rangeof variable voltage and variable frequency motor drives. It supports up to two channelsof six-independent PWM waveform

8、modulated output and others peripherals that need to be implemented in real product. This application note describes the fundamental theory and control topology of BLDC motor, and the position sensorless detection scheme based on position detectioncontrol (PDC timer module on SPMC75F2413A. Finally,

9、it shows the sensorless is cost and reliabilityeffective in comparisonwith the hall sensored solution through the experimental results.1.2SUNPLUS SPMC75F2413A Controller FeaturesThe SUNPLUS SPMC75F2413A is well suitable for digital motor control product, supports up twenty channels of PWMwaveform ou

10、tput andeight channels of duration calculation byinput capture function. It equips the u nSP kernel authored from SUNPLUS with few DSP instructions which can easily do multiply-accumulate and filter operation. This MCU offers lots of dedicated peripherals such as General-Purpose IO (GPIO, Position D

11、etection Control(PDC Timer,TPM Timer, Motor Control PWM (MCP Timer, Compare Match Timer (CMT, Standard Peripheral Interface (SPI, UART, Analog-to-Digital Converter (ADC and Watchdog Timer (WDT.The memory interface includes32K word Flash memory and 2K words SRAM memory. Following describes the detail

12、 features of SPMC75F2413A.SUNPLUS 16-bit u nSP processor (ISA 1.2Operating voltage:Core: 4.5V 5.5VOperating speed: Maximum 24MHzOperating temperature: -40 85On-chip Memory32KW (32K x 16 Flash2KW (2K x 16 SRAMOn-chip PLL based clock generationWatchdog timer10-bit analog-to-digital converter8 multiple

13、xed input channels10us (100kHz conversion timeSerial communication interfaceUART 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 A Variable-Speed Sensorless System for BLDC Motor Sunplus Technology Co., Ltd. PAGE 2 V1.1 Dec 8, 2005 SPIUp to 64 GPIO pinsPower management2 power-down modes: Wait/StandbyEach peripheral can be

14、powered down independentlyTwo Compare Match TimersFive 16-bit general-purpose timers2 for PWM, 2 for rotor speed capturing, 1 for speed loopMCP Timer channel 3 supports TIO3A-TIO3F, MCP Timer channel 4 supportsTIO4A-TIO4FPWM timers support up/down count, compare match output functionPDC Timer channe

15、l 0/1 each supports 3-channel capture input TIO0A-TIO0C andTIO1A-TIO1CTPM Timer channel 2 supports Capture/PWM compare match output functionTwelve 16-bit PWM outputs2-ch Motor drive PWM outputs (3-phase 6-pin complementary PWM outputsTIO3A-TIO3F work with MCP Timer channel 3, TIO4A-TIO4F work with M

16、CP Timerchannel 4Center- or Edge-aligned PWM outputsTemporary PWM outputs shutdown withexternal overload protection pinsEmergency PWM outputs shutdown withexternal fault protection pinsProgrammable Dead time controlPWM service and fault interrupt generationCapable of driving AC induction and BLDC mo

17、torsEmbedded In-Circuit-Emulation CircuitThe position sensorless control greatlybenefits from the PDC Timer module, MCP Timer module, and speed closed loop timer. The following describes the PDC and MCP Timers:A. PDC TimersCapability to process up to six inputs for capture or hall position input. Or

18、 six output for PWM operation.Six timer general registers (TGRAx/TGRBx/TGRCx, x = 0, 1: three registers for each channel independently assignable PWM or input capture functions.Six timer buffer registers (TBRAx/TBRBx/TBRCx, x= 0, 1 : three registers for each channel used for PWM buffering and captur

19、e operation.Selection of eight programmable clock source: six internal clocks (FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024, two external clocks (TCLKA and TCLKB. 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 A Variable-Speed Sensorless System for BLDC Motor Sunplus Technology Co., Ltd. PAGE 3 V1.1 Dec 8, 2005 Program

20、mable of timer operating modes:1. Timer counting modes:Normal counting mode: continuous up counting.PWM function: selection of 1 output, 0 output at compare match and output hold.Input capture function: selectionof issue capture at clock rising, falling, both edge,and position detection change event

21、.2. PWM mode:Three independent PWM output for each channel and can be provided with desired duty ratio. 3. Edge-aligned PWM generation mode:PWM output for normal and up counting operation.4. Center-aligned PWM generation mode:PWM output for normal and directional up-down counting operation.5. Positi

22、on detection change (PDC module:Programmable sample clock source for position signals input: four internal clocks source (FCK/4, FCK/8, FCK32 and FCK/128.Programmable position sampling mode: selection of sample position when PWM on, regularly,and lower phase are conducting current.Programmable sampl

23、ing count for position signal to avoid glitch affects the position data.Totally 14 interrupt sources:One timer period compare match interrupt and counter overflow/underflow interrupt sources. Three TGR register compare match interrupt sources.Position detection changes interrupt sources.Timer buffer

24、 operation:The input capture register can be consisted of double buffers.The PWM timer general register can automatically be modified.B. MCP TimersCapability to generate up to twelve programmable PWM waveform.Six timer general registers (TGRAx/TGRBx/TGRCx, x = 3, 4: three registers for each channel

25、independently assignable PWM compare match output functions.Six timer buffer registers (TBRAx/TBRBx/TBRCx, x= 3, 4 : three registers for each channel used for PWM buffering operation.Partial loadof duty valueof PWM generationproblem prevention: provide a load control register to make the duty value

26、for PWM could be load simultaneously.Selection of eight programmable clock source: six internal clocks (FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024, two external clocks (TCLKA and TCLKB.Programmable of timer operating modes: 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 A Variable-Speed Sensorless System for BLDC Mot

27、or Sunplus Technology Co., Ltd. PAGE 4 V1.1 Dec 8, 2005 1. Timer counting modes:Normal counting mode: continuous up counting.PWM compare match output function: selectionof 1 output, 0 output at comparematch and output hold.2. PWM mode:Two independent set of six-phase PWM output can be provided with

28、desired duty ratio.3. Edge-aligned PWM generation mode:PWM output for normal and up counting operation.4. Center-aligned PWM generation mode:Totally 10 interrupt sources, five for each channel:Timer period compare match interrupt.TGRD register compare match interrupt sources.External fault input int

29、errupt.External overload input interrupt.PWM output short protection interrupt.UVW phases output synchronization source select: synchronized to position data register P_POSx_DectData (x = 0, 1 change, TGRB or TGRC register compare match.PWM duty mode selection: use TGRA or three phase are independen

30、t.Timer buffer operation:The input capture register can be consisted of doublebuffers. The PWM compare match register can automatically be modified. 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 A Variable-Speed Sensorless System for BLDC Motor Sunplus Technology Co., Ltd. PAGE 5 V1.1 Dec 8, 2005 2Position Sensorless Con

31、trol of BLDC Motor2.1BLDC Motor and PWMThe behavior of Brushless-DC (BLDC motor is something like the DC motor but with help of electrical commutating phasewith transistor devices. There is nearly zero wiring impedance on the rotor due to the permanent magnet, so it provides good motor efficiencyin

32、comparisonwith DC and AC induction motor. The rotor flux generated from permanent magnetcan be dividedtwo kinds of waveform: trapezoidal or sinusoidal back-EMF wave shape. In this application note, the controlled motor is chosen as a trapezoidalwaveform and main control methodology is 120-degree squ

33、are wave PWM modulation. The figure 3-1 depicts the back-EMF waveform with the rotor position signals.Figure 3-1 Back-EMF vs. hall signalsIn above figure, the back-EMF zero crossing pointand hall position edge signal phase displacement can be 30 degree lead or lag.The EU, EV and EW signals are the t

34、hree-phase back-EMF and HU, HV, and HW are the three-phase rotor position signals. Thex-axis unit is the electrical degreeand everyone electrical revolution is 360 degree. Thepole-pair of the BLDC motor defines the ratio between the electrical revolution, F and the mechanical revolution, N where F i

35、s frequency in Hz and N is the speed in rpm.This is the necessary condition need for 120-degree PWM. There are totally 4 combination of 120-degree PWM waveform: upper-leg switching, lower-leg switching, pre-sixty degree switching and post-sixty degree switching 3. In this applicationnote, we select

36、the upper-legswitching PWMfor waveform generation. 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德單片機(jī)學(xué)習(xí) 資 料 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng) 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng) A Variable-Speed Sensorless System for BLDC Motorvoltage divider. The amplitude of phase voltage is range from positive half and negative half of DC-bus voltage. The resistors R114 and R119reduce the

37、 voltage level to acceptable level. The equivalent resistanceof R114 and R119 can be formed as a simple lowpass filter in combinewith C77. This filter also getsrid of high frequencysignal due to the PWM switching signals andthe output signal of stage 1 is trapezoidal shapereference to power ground.

38、According to the Bode Diagram, the phase of output waveform will be lag 90degree in comparison with IPM_MU.The circuit of stage 2 forms a high pass filter of filtering the DC component of stage 1 output signal. There is no PWM carrier signalat the output of this stageand signalis reference to a dc-o

39、ffset not the powerground. The stage 3 performs a further simple lowpass filter of stage 2 output signal.The waveform shape isbasically the same as output of stage 2.To get the neutral voltage signal of star-connection, stage 4 circuit do this task. The pseudo star connection is formed by parallelin

40、g the three phase resistor R137, R138 and R139, and the neutral voltage is feed into the negative input of comparator device. The capacitor is C91 isused to filter the noiseof neutralvoltage signal. The amplitude and frequency of neutral voltage is one-third and three times faster in comparison of o

41、ne phase voltage signal, respectively. The phase relationship between two inputs of comparator is depicts as figure 3-5.Figure 3-5 Phase relationship between comparator inputsThe signal Vn in figure 3-5 is the neutral voltage, and Eu , Ev and Ew are the three phase pseudo back-EMF signals. Through t

42、he output of comparator device, we can obtain emulated position signal of BLDC motor. The output signal of stage 5 also includes the transfer the comparator signal through an isolated opto-coupler. The signals HALL-1, HALL-2, and HALL-3 do not actually match the position signal ofBLDC motor. It has

43、the inverse polarity and different phase match characteristics 3. Also note that, this circuit is based on the back-EMF information to detect the rotor position. Thus, it is not possible to get the emulated rotorposition at stalling state. The back-EMF voltage is inducedwhen motor is in rotating sta

44、te, the 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德 單 片機(jī)學(xué) 習(xí) 資料 A Variable-Speed Sensorless System for BLDC Motorfaster of speedwill result in larger back-EMF depend oncoefficient Ke, and vice versa. Sowe need to let the motor runningwithout position signals feedback and calledin forced-commutating phase. After the electricalspe

45、ed of rotor is ten times faster than the cut-off frequencyof stage 1, therewill be 90 degree shift andwe should able to get the emulated position signal at opto-coupler output. The PDC Timers module can detectthe position signal and select different position sampling condition to suit ones applicati

46、on 1.2.3Alignment for Absolute PositionBefore the BLDC motor start to enter the forced-commutating phase, there should be a short period to let the rotor align to the user defined position. It is becausewe do not know the rotor positionwhen motor iscompletely stopped. This methodology is achieved by

47、 applying PWM signals from MCP Timer onto one upper phase and one lower phasewith certain time. The motor current will rise from zero and saturated at a level depend on applied voltage amplitude and motor s electrical time constant. It is obviously the motor current will becontrolled fineat defined

48、levelwhen we implement a current loop controller. Different motorcharacteristics and load condition should be mapping to different alignment time and voltage in order to produce enough electrical torque to align at specified location.2.4Position Sensorless Control FlowFigure 3-6 shows the state tran

49、sition when motor is from stalling to running. First, the system driverneeds to charge the bootstrap voltage in order to supply the upper phase a gate source. It is implemented byturn on all the transistor device at lower phase simultaneously with a certain time to meet the charging parameters of bo

50、otstrap circuit.Then makethe rotor align to a user defined location. After all these actiondone successfully, one needs to make the motor start to run to an specified open loop speedwithout positionfeedback. This is achieved by increasing thePWM dutyratio value and change the pseudo position signal

51、insystem driver. When the motor rotates and able to sample correct positionsignal for several times, ones canswitch from non-position feedback condition to position feedback rotating state. At this stage the speedcan be well controlled and also the commutating phase. 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng)諾德 單 片機(jī)學(xué) 習(xí) 資料 專業(yè)單片機(jī)、

52、計(jì)算機(jī)資料網(wǎng) 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng) 專業(yè)單片機(jī)、計(jì)算機(jī)資料網(wǎng) A Variable-Speed Sensorless System for BLDC Motor Sunplus Technology Co., Ltd. PAGE 13 V1.1 Dec 8, 2005 The emulated position signal from sensorless circuit, there may exist certain noise on the rising and falling edge of the position signal. In figure 4-3, the glitc

53、h interval is about144us. If there is no filter circuit to remove the glitch, the high-low transition may result in wrong phase commutation and incorrect speed information. In the PDC timermodule of SPMC75F2413A, the position sampling clock, counter and condition are all programmable. In such condition, user only needsto setup the SPLCK, SPLMOD, and SPLCNT to be able to remove this kind of gl