課程設(shè)計(jì)基于FPGA的出租車計(jì)價(jià)器設(shè)計(jì)

1、基于fpga的出租車計(jì)價(jià)器設(shè)計(jì)摘 要介紹了出租車計(jì)費(fèi)器系統(tǒng)的組成及工作原理，簡(jiǎn)述了在eda平臺(tái)上用fpga器件構(gòu)成該數(shù)字系統(tǒng)的設(shè)計(jì)思想和實(shí)現(xiàn)過(guò)程。論述了計(jì)程模塊，計(jì)費(fèi)模塊，計(jì)時(shí)模塊，譯碼動(dòng)態(tài)掃描模塊等的設(shè)計(jì)方法與技巧。 1引言隨著eda技術(shù)的高速發(fā)展，電子系統(tǒng)的設(shè)計(jì)技術(shù)發(fā)生了深刻的變化，大規(guī)?？删幊踢壿嬈骷pldfpga的出現(xiàn)，給設(shè)計(jì)人員帶來(lái)了諸多方便。利用它進(jìn)行產(chǎn)品開(kāi)發(fā)，不僅成本低、周期短、可靠性高，而且具有完全的知識(shí)產(chǎn)權(quán)。本文介紹了一個(gè)以altera公司可編程邏輯芯片cyclone2系列的ep2c5t144c8的fpga芯片為控制核心、附加一定外圍電路組成的出租車計(jì)費(fèi)器系統(tǒng)。隨著社會(huì)的不

2、斷進(jìn)步，人們生活水平的不斷提高，出租車逐漸成為人們?nèi)粘Ｉ畈豢扇鄙俚慕煌üぞ?。而?jì)價(jià)器作為出租車的一個(gè)重要組成部分，關(guān)系著出租車司機(jī)和乘客雙方利益，起著重要的作用，因而出租車計(jì)價(jià)器的發(fā)展非常迅猛。2出租車計(jì)費(fèi)系統(tǒng)的實(shí)驗(yàn)任務(wù)及要求2.1技術(shù)要求（1）掌握較復(fù)雜邏輯的設(shè)計(jì)、調(diào)試。（2）進(jìn)一步掌握用vhdl語(yǔ)言設(shè)計(jì)數(shù)字邏輯電路。（3）掌握用max+pulsii軟件的原理圖輸入的設(shè)計(jì)方法。2.2功能要求基本功能：（1）按行駛里程收費(fèi)，起步價(jià)為9.00元，并在車行3公里后再按3元/公里計(jì)算車費(fèi)。（2）實(shí)現(xiàn)模擬功能：能模擬汽車啟動(dòng)、停止。（3）設(shè)計(jì)動(dòng)態(tài)掃描電路：將車費(fèi)、里程、等待時(shí)間動(dòng)態(tài)的顯示出來(lái)。（4）

3、用vhdl語(yǔ)言設(shè)計(jì)符合上述功能要求的出租車計(jì)費(fèi)器，并用層次化設(shè)計(jì)方法設(shè)計(jì)該電路。（5）各計(jì)數(shù)器的計(jì)數(shù)狀態(tài)用功能仿真的方法驗(yàn)證，并通過(guò)有關(guān)波形確認(rèn)電路設(shè)計(jì)是否正確。附加功能：（1）增加了晚上計(jì)費(fèi)功能和等待功能。晚上起步價(jià)為12.00元，并在車行3公里后再按4元/公里計(jì)算車費(fèi)。車白天停止超過(guò)三分鐘后按1元/分鐘計(jì)算，晚上超過(guò)3分鐘按2元/分鐘計(jì)算。（2）實(shí)現(xiàn)預(yù)置功能：能預(yù)置起步費(fèi)、每公里收費(fèi)、等待加費(fèi)時(shí)間。（3）實(shí)現(xiàn)模擬功能：白天、黑夜；等待、行駛狀態(tài)。（4）設(shè)計(jì)超過(guò)三公里提醒功能。2.3本人任務(wù)本人負(fù)責(zé)軟件部分。2.4任務(wù)書(shū)（附錄一）3.方案設(shè)計(jì)及原理框圖3.1硬件方案設(shè)計(jì)及原理框圖硬件系統(tǒng)組成

4、框圖開(kāi)關(guān)電路fpga模塊動(dòng)態(tài)顯示電路各模塊的作用和組成：（1）開(kāi)關(guān)模塊該模塊的作用是用于電路的輸入的信號(hào)。主要有三個(gè)開(kāi)關(guān)以及三個(gè)限流電阻,電源構(gòu)成。（3）動(dòng)態(tài)顯示模塊:此模塊由六個(gè)數(shù)碼管和三個(gè)二極管所構(gòu)成，17個(gè)200電阻起到限制電流的作用，使得流到數(shù)碼管的電流適當(dāng)，防止數(shù)碼管中的電流過(guò)大，而使得數(shù)碼管損壞。數(shù)碼管將計(jì)費(fèi)、等待時(shí)間和里程動(dòng)態(tài)的顯示出來(lái)。3.2軟件方案設(shè)計(jì)及原理框圖3.2.1系統(tǒng)的頂層框圖及方案設(shè)計(jì)：動(dòng)態(tài)顯示模塊控制芯片信號(hào)輸入 信號(hào)輸入：各種控制信號(hào)經(jīng)輸入端給控制芯片?？刂菩酒翰捎玫挠衏pld或者fpga等。動(dòng)態(tài)顯示電路：采用的是數(shù)碼管來(lái)實(shí)現(xiàn)功能的輸出。3.2.2 fpga內(nèi)

5、部具體框圖及方案設(shè)計(jì)：出租車的一般計(jì)費(fèi)過(guò)程為：出租車載客后，啟動(dòng)計(jì)費(fèi)器，整個(gè)系統(tǒng)開(kāi)始運(yùn)行，里程計(jì)數(shù)器從0開(kāi)始計(jì)數(shù)，費(fèi)用計(jì)數(shù)器從9開(kāi)始計(jì)算；出租車載客中途等待，等待時(shí)間計(jì)數(shù)器從0開(kāi)始計(jì)數(shù)。最后根據(jù)行駛里程或停止等待的時(shí)間的計(jì)費(fèi)標(biāo)準(zhǔn)計(jì)費(fèi)。出租車到達(dá)目的地停止后，停止計(jì)費(fèi)器，顯示總費(fèi)用。根據(jù)出租車計(jì)費(fèi)器的工作過(guò)程，本系統(tǒng)采用分層次、分模塊的方式設(shè)計(jì)，其fpga內(nèi)部具體框圖如下所示。輸入信號(hào)分頻器車費(fèi)計(jì)數(shù)模塊車行駛狀態(tài)譯碼模塊輸出控制模塊里程計(jì)數(shù)模塊各模塊的功能：(1)由fpga晶振電路產(chǎn)生50mhz時(shí)鐘信號(hào)并輸入。(2)分頻器：將時(shí)鐘信號(hào)進(jìn)行分頻。(3)標(biāo)志模塊：將按鈕產(chǎn)生的脈沖轉(zhuǎn)化為一種標(biāo)志信號(hào)。

6、(4)計(jì)程模塊：在等待信號(hào)未作用時(shí)，來(lái)一個(gè)時(shí)鐘脈沖信號(hào)，里程值加1。該模塊還包含一個(gè)路程計(jì)費(fèi)標(biāo)志的小模塊，輸出一個(gè)路程計(jì)費(fèi)的信號(hào)。(5）等待狀態(tài)模塊：等待信號(hào)作用時(shí)，該模塊可以記錄等待的時(shí)間，并產(chǎn)生等待計(jì)費(fèi)的信號(hào)。(6）車費(fèi)計(jì)數(shù)模塊：按行駛里程收費(fèi)，分為白天和黑夜。白天收費(fèi)標(biāo)準(zhǔn)：起步費(fèi)為12.00元，超過(guò)3公里按4元/公里，車暫停超過(guò)三分鐘按2元/分鐘計(jì)算。黑夜收費(fèi)標(biāo)準(zhǔn)：起步費(fèi)為15.00元，超過(guò)3公里按5元/公里，車暫停超過(guò)三分鐘按1元/分鐘計(jì)算。(7）輸出控制模塊：分時(shí)輸出里程、等待時(shí)間、費(fèi)用三個(gè)信號(hào)，實(shí)現(xiàn)動(dòng)態(tài)顯示功能。(8）譯碼模塊：實(shí)現(xiàn)將車費(fèi)計(jì)數(shù)模塊、等待狀態(tài)模塊和里程計(jì)數(shù)模塊輸出的b

7、cd碼轉(zhuǎn)換成七段碼輸出。4.各單元模塊設(shè)計(jì)，仿真結(jié)果及分析本系統(tǒng)采用層次化、模塊化的設(shè)計(jì)方法，設(shè)計(jì)順序?yàn)樽韵孪蛏稀Ｊ紫葘?shí)現(xiàn)系統(tǒng)框圖中的各子模塊，然后由頂層模塊調(diào)用各子模塊來(lái)完成整個(gè)系統(tǒng)。4.1分頻模塊：4.1.1分頻模塊的框圖圖3.1.1分頻器的實(shí)體圖此模塊的功能是對(duì)總的時(shí)鐘進(jìn)行分頻，總的時(shí)鐘是50m。計(jì)數(shù)分頻器使用五個(gè)這樣基本的分頻器（35分頻）組合而成，控制模塊分頻器使用三個(gè)這樣基本的分頻器（35分頻）組合而成。4.1.2分頻模塊的vhdl程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;e

8、ntity pulse is port(clk0:in std_logic; fout:out std_logic);end pulse;architecture one of pulse isbegin process(clk0) variable cnt:std_logic_vector(2 downto 0); variable full :std_logic; begin if clk0'event and clk0='1' then if cnt="100" then cnt:="000" ; full:='1&

9、#39; else cnt:=cnt+1; full:='0' end if; end if;fout<=full;end process;end one;4.1.3仿真的結(jié)果從該波形圖可以看出輸入脈沖的頻率是輸出脈沖的頻率的35倍。4.2計(jì)程模塊：4.2.1計(jì)程模塊的框圖：此模塊的功能是計(jì)算出租車行駛的路程。在出租車啟動(dòng)并行駛的過(guò)程中(開(kāi)始/結(jié)束信號(hào)ss為1，行駛/等待信號(hào)wr為1)，當(dāng)時(shí)鐘clks是上升沿的時(shí)候，系統(tǒng)即對(duì)路程計(jì)數(shù)器jc的里程計(jì)數(shù)器進(jìn)行加計(jì)數(shù)，當(dāng)路程超過(guò)三公里時(shí)，系統(tǒng)將輸出標(biāo)志正脈沖lcjfbz。4.2.2計(jì)程模塊的vhdl程序(1) 計(jì)程程序libra

10、ry ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jc is port(clks,ss,wr:in std_logic; lc:buffer std_logic_vector(7 downto 0); end entity jc;architecture one of jc is signal q1,q0:std_logic_vector(3 downto 0);beginprocess(clks,ss,wr,lc) variable sw:std_logic_vector(1 downto 0

11、); begin sw:=ss&wr; if sw="00" or sw="01" then q1<="0000"q0<="0000" elsif sw="11" then q1<=q1;q0<=q0; elsif clks'event and clks='1' then if q1=9 and q0=9 then q1<="0000"q0<="0000" elsif q0=9 then

12、q1<=q1+1;q0<="0000" else q1<=q1;q0<=q0+1; end if; end if;end process;(2) 計(jì)程標(biāo)志程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity lcjfbz is port(ss:in std_logic; -ss開(kāi)始/復(fù)位信號(hào), lc:in std_logic_vector(7 downto 0); lcjfbz:out std_logic); end entity lcjfb

13、z;architecture two of lcjfbz is begin process(ss,lc) begin if ss='0' or (lc(7 downto 4)="0000" and lc(3 downto 0)<4) then lcjfbz<='0' else lcjfbz<='1' end if; end process;end two;4.2.3計(jì)程模塊仿真結(jié)果：從波形圖可以看出在時(shí)鐘的控制下當(dāng)ss為低電平的時(shí)候lc為零，當(dāng)ss為高電平且wr為高電平的時(shí)候lc開(kāi)始計(jì)數(shù)，當(dāng)計(jì)到大于三的時(shí)候輸

14、出了lcjfbz為高電平。4.3計(jì)時(shí)模塊：4.3.1計(jì)時(shí)模塊的框圖：此模塊用于計(jì)算停車等待的時(shí)間。在出租車行進(jìn)中，如果車輛停止等待，計(jì)數(shù)器則在信號(hào)clk的上升沿進(jìn)行加計(jì)數(shù)，當(dāng)累計(jì)等待時(shí)間超過(guò)2（不包括2分鐘）分鐘時(shí)，輸出標(biāo)志ddjfbz正脈沖信號(hào)。4.3.2計(jì)時(shí)模塊的vhdl程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ddzt is port(clk,ss:in std_logic; ddbz:in std_logic; ddjfbz:out std_logic; ddsj

15、:out std_logic_vector(7 downto 0);end entity ddzt;architecture one of ddzt isbegin process(clk,ss,ddbz) variable q1,q0: std_logic_vector(3 downto 0); begin if ss='0' then q1:="0000"q0:="0000"ddjfbz<='0' elsif ddbz='1' then if clk='1' and clk'

16、;event then if q1=9 and q0=9 then q1:="0000"q0:="0000" elsif q0=9 then q1:=q1+1;q0:="0000" else q1:=q1;q0:=q0+1; end if; if(q1>0 or q0>3) then ddjfbz<='1' end if; end if; end if; ddsj(7 downto 4)<=q1;ddsj(3 downto 0)<=q0;end process;end one;4.3.3計(jì)

17、時(shí)模塊的仿真結(jié)果：從波形圖可以看出在clk的控制下當(dāng)ss為高電平ddbz為高電平的時(shí)候時(shí)間計(jì)數(shù)但是費(fèi)用沒(méi)有計(jì)數(shù)，ddjfbz為低電平。4.4計(jì)費(fèi)模塊:4.4.1計(jì)費(fèi)模塊的框圖：費(fèi)用計(jì)數(shù)器模塊用于出租車啟動(dòng)后，根據(jù)行駛路程和等待時(shí)間計(jì)算費(fèi)用。當(dāng)出租車啟動(dòng)時(shí)，ss為高電平，用于將費(fèi)用計(jì)數(shù)器復(fù)位為起步價(jià)10元；當(dāng)車處于行駛狀態(tài)且滿3公里時(shí)，select_clk信號(hào)選擇distans_enable，此后路程每滿1公里，費(fèi)用計(jì)數(shù)器加1元；當(dāng)出租車處于停止等待狀態(tài)且時(shí)鐘滿2分鐘時(shí)，select_clk信號(hào)選擇time_enable信號(hào)，時(shí)間每滿1分鐘，費(fèi)用計(jì)數(shù)器加1元。4.4.2計(jì)費(fèi)模塊的vhdl的程序：

18、library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;-定義函數(shù)名package packexp1 is function bcd_add8(ain,bin : in std_logic_vector) return std_logic_vector;end;-描述函數(shù)體package body packexp1 is function bcd_add8(ain,bin : std_logic_vector) return std_logic_vector is type type_bcdx4 is a

19、rray(3 downto 0) of std_logic_vector(4 downto 0); variable sa,sb : type_bcdx4; variable ci : std_logic_vector(4 downto 0); variable sout : std_logic_vector(11 downto 0); begin ci:=(others=>'0'); sout:=(others=>'0'); for i in 0 to 1 loop -0-1的循環(huán) sa(i) := ('0' & ain(i

20、*4+3 downto i*4)+('0' & bin(i*4+3 downto i*4)+("0000" & ci(i); if (sa(i)(4)='1') or (sa(i)(3 downto 0)>9) then sb(i) := sa(i) + "00110" else sb(i) := sa(i); end if; ci(i+1) := sb(i)(4); sout(i*4+4 downto i*4):=sb(i); end loop; return sout;end function b

21、cd_add8;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.packexp1.all;entity jf is port( ss:in std_logic; -開(kāi)始/停止信號(hào),低電平停止，高電平開(kāi)始 dn:in std_logic; -白天黑夜控制，高電平夜間，低電平白天 lc:in std_logic_vector(7 downto 0); - 路程 ddsj:in std_logic_vector(7 downto 0); -等待時(shí)間 lcjfbz:in std_

22、logic; -路程計(jì)費(fèi)標(biāo)志 ddjfbz:in std_logic; -等待計(jì)費(fèi)標(biāo)志，高電平時(shí)等待開(kāi)始計(jì)費(fèi)，低電平不計(jì)費(fèi) fy:out std_logic_vector(7 downto 0); -總費(fèi)用end entity jf;architecture one of jf is begin - 討論白天/黑夜？路程計(jì)費(fèi)？等待計(jì)費(fèi)？ process(ss,dn,lc,ddsj,ddjfbz,lcjfbz) variable fy1 :std_logic_vector(11 downto 0); begin if ss='0' then fy1:="00000000

23、0000" elsif dn='0' then -白天時(shí) if lcjfbz='0' then -起始價(jià) fy1(11 downto 4):=(others=>'0'); -9 fy1(3 downto 0):="1001" else -加收路程費(fèi) fy1:=bcd_add8(lc,lc); fy1:=bcd_add8(fy1,lc); -多一個(gè)脈沖加收3，則變成lc*3 end if; elsif lcjfbz='0' then -起始價(jià) fy1(11 downto 5):=(others=&

24、gt;'0'); fy1(4 downto 0):="10010" -12 else fy1:=bcd_add8(lc,lc); fy1:=bcd_add8(fy1,lc); fy1:=bcd_add8(fy1,lc); -每一個(gè)脈沖加收4，則變成lc*4 end if; if dn='0' then -白天時(shí) if ddjfbz='0' then -未到等待收費(fèi)時(shí)間 fy1:=fy1; -不加收 else -加收路程費(fèi) fy1:=bcd_add8(fy1,ddsj); fy1:=bcd_add8(fy1,ddsj); -一超

25、過(guò)等待收費(fèi)時(shí)間，就立即加收等待時(shí)的每個(gè)脈沖加2 end if; elsif ddjfbz='0' then -未到等待收費(fèi)時(shí)間 fy1:=fy1; -不加收 else -加收路程費(fèi) fy1:=bcd_add8(fy1,ddsj); -一超過(guò)等待收費(fèi)時(shí)間，就立即加收等待時(shí)的每個(gè)脈沖加1 end if; fy<=fy1(7 downto 0); end process;end one;4.4.3計(jì)費(fèi)模塊的仿真結(jié)果：白天模式黑夜模式從波形圖可以看出dn為高電平選擇白天模式進(jìn)行計(jì)費(fèi)，dn為低電平選擇黑夜模式進(jìn)行計(jì)費(fèi)。4.5數(shù)碼管顯示模塊：4.5.1數(shù)碼管顯示模塊的框圖：4.5.2

26、數(shù)碼管顯示的vhdl程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity ymq isport(din:in std_logic_vector(7 downto 0); dout1:out std_logic_vector(6 downto 0); dout0:out std_logic_vector(6 downto 0);end entity ymq;architecture one of ymq isbeginproce

27、ss(din)begin case din(7 downto 4) is when "0000" =>dout1<="1111110" when "0001" =>dout1<="0110000" when "0010" =>dout1<="1101101" when "0011" =>dout1<="1111001" when "0100" =>dout1<

28、;="0110011" when "0101" =>dout1<="1011011" when "0110" =>dout1<="1011111" when "0111" =>dout1<="1110000" when "1000" =>dout1<="1111111" when "1001" =>dout1<="1111011

29、" when others =>dout1<="0000000"end case; case din(3 downto 0) is when "0000" =>dout0<="1111110" when "0001" =>dout0<="0110000" when "0010" =>dout0<="1101101" when "0011" =>dout0<="

30、;1111001" when "0100" =>dout0<="0110011" when "0101" =>dout0<="1011011" when "0110" =>dout0<="1011111" when "0111" =>dout0<="1110000" when "1000" =>dout0<="1111111"

31、when "1001" =>dout0<="1111011" when others =>dout0<="0000000"end case;end process;end one;4.5.3數(shù)碼管顯示模塊的仿真結(jié)果：4.6控制模塊：4.6.1控制模塊的框圖：控制模塊用于對(duì)數(shù)碼管里程、時(shí)間、費(fèi)用顯示的選擇，起到位選的作用，實(shí)現(xiàn)了數(shù)碼管動(dòng)態(tài)顯示，節(jié)省了芯片的資源。4.6.2控制模塊的vhdl程序：(1)sel1模塊library ieee;use ieee.std_logic_1164.all;use ieee.s

32、td_logic_unsigned.all;entity sel1 is port(clk1:in std_logic; s1:out std_logic_vector(1 downto 0);end sel1;architecture sel_arc of sel1 isbegin process(clk1) variable cnt:std_logic_vector(1 downto 0);begin if clk1'event and clk1='1' then if cnt="10" then cnt:="00" else

33、 cnt:=cnt+1; end if; end if;s1<=cnt;end process;end sel_arc;(2)sel2模塊library ieee;use ieee.std_logic_1164.all;entity sel2 isport(sel2:in std_logic_vector(1 downto 0); s2:out std_logic_vector(2 downto 0);end sel2;architecture bbb_arc of sel2 isbegin process(sel2)begincase sel2 is when "00&quo

34、t;=>s2<="110" when "01"=>s2<="101" when "10"=>s2<="011" when others=>s2<="zzz"end case;end process;end bbb_arc;4.6.3控制模塊的仿真結(jié)果：(1)sel1模塊(2)sel2模塊從波形圖可以看出當(dāng)片選信號(hào)是00時(shí)，輸出選擇記程輸出。當(dāng)片選信號(hào)是01時(shí)，輸出選擇記費(fèi)輸出。當(dāng)片選信號(hào)是10時(shí)，輸出選擇等到時(shí)間輸出。5.頂層模

35、塊設(shè)計(jì)，仿真結(jié)果及分析各模塊設(shè)計(jì)仿真實(shí)現(xiàn)后，可分別創(chuàng)建成元件符號(hào)。頂層就是將各分模塊用vhdl語(yǔ)言或者是圖形方法連接起來(lái)，便可實(shí)現(xiàn)系統(tǒng)電路。5.1頂層模塊的vhdl程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity czc isport(clk,wr,ss,dn:in std_logic; dnpd:out std_logic; shuc1,shuc0:out std_logic_vector(6 downto 0); we

36、ix:out std_logic_vector(2 downto 0);end entity czc;architecture one of czc iscomponent bzport(aj:in std_logic; bz:out std_logic);end component;component pulse port(clk0:in std_logic; fout:out std_logic);end component;component ddzt port(clk,ss:in std_logic; ddbz:in std_logic; ddjfbz:out std_logic;待添

37、加的隱藏文字內(nèi)容2 ddsj:out std_logic_vector(7 downto 0);end component;component jcport(clks,ss,wr:in std_logic; lc:buffer std_logic_vector(7 downto 0);end component;component lcjfbzport(ss:in std_logic; lc:in std_logic_vector(7 downto 0); lcjfbz:out std_logic); end component;component jf port( ss:in std_log

38、ic; dn:in std_logic; lc:in std_logic_vector(7 downto 0); ddsj:in std_logic_vector(7 downto 0); lcjfbz:in std_logic; ddjfbz:in std_logic; fy:out std_logic_vector(7 downto 0); end component;component ymqport(din:in std_logic_vector(7 downto 0); dout1:out std_logic_vector(6 downto 0); dout0:out std_log

39、ic_vector(6 downto 0);end component;component xzscport(jc,jf,wt:in std_logic_vector(7 downto 0);sel:in std_logic_vector(1 downto 0);q:out std_logic_vector(7 downto 0);end component;component sel1port(clk1:in std_logic;s1:out std_logic_vector(1 downto 0);end component;component sel2port(sel2:in std_l

40、ogic_vector(1 downto 0);s2:out std_logic_vector(2 downto 0);end component;signal a,b,c,d,e,f,i,j,m,n:std_logic;signal x,y,z,w:std_logic_vector(7 downto 0);signal k:std_logic_vector(1 downto 0); begindnpd<=a;u1:bz port map(aj=>dn,bz=>a);u2:bz port map(aj=>ss,bz=>b);u3:bz port map(aj=&g

41、t;wr,bz=>c);u4:pulse port map(clk0=>clk,fout=>d);u5:pulse port map(clk0=>d,fout=>i);u6:pulse port map(clk0=>i,fout=>j);u7:pulse port map(clk0=>j,fout=>m);u8:pulse port map(clk0=>m,fout=>n);u9:jc port map(clks=>n,ss=>b,wr=>c,lc=>z);u10:ddzt port map(clk=&g

42、t;n,ss=>b,ddbz=>c,ddjfbz=>f,ddsj=>y);u11:lcjfbz port map(ss=>b,lc=>z,lcjfbz=>e);u12:jf port map(ss=>b,dn=>a,lc=>z,ddsj=>y,lcjfbz=>e,ddjfbz=>f,fy=>x);u13:xzsc port map(jf=>x,jc=>z,wt=>y,sel=>k,q=>w);u14:sel1 port map(clk1=>j,s1=>k);u15:se

43、l2 port map(sel2=>k,s2=>weix);u16:ymq port map(din=>w,dout1=>shuc1,dout0=>shuc0);end architecture one;5.2波形仿真5.3輸入、輸出信號(hào)說(shuō)明輸入：dn:day or night控制；ss:start or stop控制；wr:wait or run控制；clk:輸入時(shí)鐘信號(hào)，模擬時(shí)間和路程。輸出：dnpb：用于判別白天還是黑夜的輸出信號(hào)，接至發(fā)光二極管，白天不發(fā)光，黑夜的時(shí)候發(fā)光。fy1:費(fèi)用的十位fy0:費(fèi)用的個(gè)位ddsj1:等待時(shí)間的十位ddsj0:等待時(shí)間的

44、個(gè)位lc1:路程的十位lc0:路程的個(gè)位5.4各個(gè)模塊的軟件連線圖（見(jiàn)附錄二）6硬件電路設(shè)計(jì)與安裝圖6.1硬件電路設(shè)計(jì)圖（見(jiàn)附錄三）6.2硬件電路的元器件清單：器件名稱及個(gè)數(shù)杜邦線若干根電阻200歐姆21個(gè)1k3個(gè)20腳底座3個(gè)插針若干個(gè)90123個(gè)發(fā)光二極管1個(gè)數(shù)碼管6個(gè)按鈕開(kāi)關(guān)3個(gè)芯片fpga導(dǎo)線若干根7硬件電路安裝與調(diào)試7.1硬件電路安裝與調(diào)試的步驟（1）根據(jù)硬件電路圖在通用板上布線（2）檢查元器件的好壞，確保每一個(gè)元器件是好的才能進(jìn)行焊接(焊接時(shí)要注意虛焊，短路等等)（3）焊好之后要根據(jù)安裝圖用萬(wàn)用表進(jìn)行測(cè)量，防止電路存在錯(cuò)誤(注意焊接要仔細(xì))7.2調(diào)試過(guò)程中的困難（1）接入5伏電壓之

45、后，開(kāi)關(guān)模塊中有一個(gè)按鈕不能起作用，通過(guò)萬(wàn)用表檢測(cè)，發(fā)現(xiàn)有一個(gè)點(diǎn)沒(méi)有連接上。（3）軟硬件連接時(shí)，數(shù)碼管顯示亂碼。我們反復(fù)檢查程序后發(fā)現(xiàn)數(shù)碼管ag的硬件引腳與軟件引腳接反了。最后，我們重新連接了引腳，達(dá)到了預(yù)期的效果。8調(diào)試結(jié)果說(shuō)明及分析dn不按下（即發(fā)光二極管不亮），說(shuō)明是白天狀態(tài)：（1）按下ss，計(jì)費(fèi)數(shù)碼管顯示09，記程數(shù)碼管開(kāi)始變化。隨著記程數(shù)碼管顯示的數(shù)值超過(guò)3公里后，計(jì)費(fèi)數(shù)碼管按超出每公里3元計(jì)算。（2）再按下wr，等待時(shí)間數(shù)碼管開(kāi)始計(jì)數(shù)，記程、計(jì)費(fèi)數(shù)碼管均保持不變，當(dāng)?shù)却龝r(shí)間超過(guò)3分鐘后，計(jì)費(fèi)數(shù)碼管按超出每分鐘2元計(jì)算，記程數(shù)碼管仍保持不變。（3）再按wr，計(jì)費(fèi)、記程數(shù)碼管再次發(fā)生變

46、化。（4）再按下ss清零。dn按下（即發(fā)光二極管發(fā)光），說(shuō)明是黑夜?fàn)顟B(tài)：（1）按下ss，計(jì)費(fèi)數(shù)碼管顯示12，記程數(shù)碼管開(kāi)始變化。隨著記程數(shù)碼管顯示的數(shù)值超過(guò)3公里后，計(jì)費(fèi)數(shù)碼管按超出每公里4元計(jì)算。（2）再按下wr，等待時(shí)間數(shù)碼管開(kāi)始計(jì)數(shù)，記程、計(jì)費(fèi)數(shù)碼管均保持不變，當(dāng)?shù)却龝r(shí)間超過(guò)3分鐘后，計(jì)費(fèi)數(shù)碼管按超出每分鐘1元計(jì)算，記程數(shù)碼管仍保持不變。（3）再按wr，計(jì)費(fèi)、記程數(shù)碼管再次發(fā)生變化。9收獲體會(huì)經(jīng)過(guò)兩個(gè)星期的課程設(shè)計(jì)，我收益頗多。不僅增強(qiáng)了個(gè)人的實(shí)踐能力，也增強(qiáng)了個(gè)人與團(tuán)體的凝聚力，以及學(xué)會(huì)了在問(wèn)題中不斷探索，不斷學(xué)習(xí)，不斷創(chuàng)新的毅力。10.結(jié)束語(yǔ)本文介紹了一種全新的出租車計(jì)價(jià)器計(jì)費(fèi)系統(tǒng)的

47、fpga設(shè)計(jì)方法。如果將該設(shè)計(jì)再結(jié)合到實(shí)際應(yīng)用中，那么，只需改變?cè)O(shè)計(jì)中計(jì)費(fèi)要求，就可以應(yīng)用到出租車上。另外，如果可實(shí)現(xiàn)任意輸入該出租車計(jì)價(jià)器的計(jì)費(fèi)標(biāo)準(zhǔn)的功能，那么，它的適用范圍可能就更廣泛了。11.參考文獻(xiàn):1 夏宇聞，verloghdl 數(shù)字系統(tǒng)設(shè)計(jì)教程,北京航空航天大學(xué)出版社。2 杜慧敏，基于veriloghdl的fpga設(shè)計(jì)基礎(chǔ)，西安電子科技大學(xué)出版社。employment tribunals sort out disagreements between employers and employees.you may need to make a claim to an employme

48、nt tribunal if:· you don't agree with the disciplinary action your employer has taken against you· your employer dismisses you and you think that you have been dismissed unfairly.for more information about dismissal and unfair dismissal, see dismissal.you can make a claim to an em

49、ployment tribunal, even if you haven't appealed against the disciplinary action your employer has taken against you. however, if you win your case, the tribunal may reduce any compensation awarded to you as a result of your failure to appeal.remember that in most cases you must make an

50、 application to an employment tribunal within three months of the date when the event you are complaining about happened. if your application is received after this time limit, the tribunal will not usually accept it.if you are worried about how the time limits apply to you, take advice from one of

51、the organisations listed under further help.employment tribunals are less formal than some other courts, but it is still a legal process and you will need to give evidence under an oath or affirmation.most people find making a claim to an employment tribunal challenging. if you are thinking abo

52、ut making a claim to an employment tribunal, you should get help straight away from one of the organisations listed under further help.if you are being represented by a solicitor at the tribunal, they may ask you to sign an agreement where you pay their fee out of your compensation if you win t

53、he case. this is known as a damages-based agreement. in england and wales, your solicitor can't charge you more than 35% of your compensation  if you win the case.if you are thinking about signing up for  a damages-based agreement, you should make sure you're clear about the t

54、erms of the agreement. it might be best to get advice from an experienced adviser, for example, at a citizens advice bureau.  to find your nearest cab, including those that give advice by e-mail, click on nearest cab.for more information about making a claim to an employment tribunal, see&

55、#160;employment tribunals.the (lack of) air up there watch mcayman islands-based webb, the head of fifa's anti-racism taskforce, is in london for the football association's 150th anniversary celebrations and will attend city's premier league match at chelsea on sunday."i am going to

56、 be at the match tomorrow and i have asked to meet yaya toure," he told bbc sport."for me it's about how he felt and i would like to speak to him first to find out what his experience was."uefa has opened disciplinary proceedings against cska for the "racist behaviour of their fans" during city's 2-1 win.michel platini, president of european football's governing body, has also ordered an immediate investigation into the referee's actions.cska said they were "surprised and disappointed" by toure's compla