直接數(shù)字頻率合成器固件開發(fā)結

1、A Direct Digital SynthesisFirmware Development FrameworkI. JIVET, B. DRAGOI, M. OTESTEANU,L. JURCA Applied Electronics Department University“Politechnica” Timisoara V. Parvan 2, TimisoaraROMANIAAbstract: - The paper presents a development framework for direct digital signal synthesis targeting FPGA

2、using the novel amplitude sequencing architecture. An analysis of the frequency purity and timing characteristics of the architecture is presented as key elements in the design process. An emulator for the generator circuit using the Xilinx picoBlaze microprocessor is proposed as a development frame

3、work in early design. The emulation of the generator in Xilinx picoBlaze code for single and double byte word length was used. Timing delays for the generator module were implemented as add on logic. The design of a three frequencies pack synthesizer using the integrated development environment is p

4、resented as a practical validation test. The flexible solutiondetermined using the framework for a three frequency case sample application exemplifies the versatility of the proposed framework.Keywords: amplitude based DDFS, picoBlaze emulated frequency synthesis, DDFS development framework1 Introdu

5、ctionDirect digital synthesis is a technique that has been adopted in many fields of applications due to the advantages and characteristics hard to match with classical analog solutions 14. The technology of choice for prototype or final implementation is shifting increasingly to FPGA devises 6. The

6、 classical DDFS phase accumulator architecture has one major drawback in the explosive ROM size necessary in the case of high resolution signals. The literature in recent years presents new architectures promoting different methods to generate sine/cosine signals among which the CORDIC or angle rota

7、tion algorithms are more frequently used 4 5. A novel architecture based on algorithmic amplitude generation was proposed recently that distinguishes from the rest by its very efficientimplementation 1. Designing with DDFS cores is not a simple task due to the need of tuning the architecture to a pa

8、rticular application. Exploration of the design space and configuration of the architecture led solution providers to offer specialized software tools for the task 89. The paper introduces a development environment for the amplitude based DDFS architecture. The main characteristics of the architectu

9、re are reviewed from the design process perspective. An in depth analysis of architecture output capabilities like frequency purity and phase timing compensation is also given. A PicoBlaze emulation environment is introduced as a tool in the design process to help in the design space exploration for

10、 the amplitude based architecture. The framework provides a versatile mean for tuning the architecture and variable tracking in the design process. Finally a design case for a sample application using the proposed environment is also presented as a proof of concept. Further work needed and conclusio

11、ns are presented in the final part of the paper.2 Amplitude Based DDFS ArchitectureThe distinctive characteristic of the DDFS amplitude based architecture is the replacement of the phase to sine look up table translator module by a direct algorithmic amplitude generating core. The module generates a

12、lgorithmically sequences of values by tracking the trajectory of a rotating vector on a circle, in a Cartesian coordinate frame. The successive vector positions projections on the two axis form the sine and cosine value sequences.It is known since the original paper that the sample values are non un

13、iformly distributed with respect to phase5. Immediate use of the algorithmically determined values under uniform timing for the generation of sine and cosine samples results in phase distortions of the generated signal. The extension of the algorithm with a correction in the phase for the use in sin

14、e and cosine function sequences generation is the following:Loop:Select the x or y direction for the next step; Generate coordinates, as sampled values for sine and cosine functions; Determine the phase angle advancement; Output samples with sample timing delay; For an opposite axis step keep the sa

15、mple value constant.End Loop; In Fig. 1 a block diagram of the architecture is presented indicating the main modules and associated input control words. The algorithm receives as inputs AT and FT, respectively the amplitude and frequency tuning words of length n, m. Register r and counters c impleme

16、nt storage and general system clock Ckcounting. The x, y phase compensations counters c resolution can be adjusted to any value smaller then n trading accuracy to higher maximum generated signalfrequency. The most sensitive element in the DDFS architecture remains the DAC converter and its linearity

17、 for wide word length in order to generate pure signals.Fig.1 Amplitude based DDFS architecture block diagram with two input tuning words for amplitude and frequency. Fig . 2. S ymmetric manualimplementation of the amplitude generator algorithm at RTL level.As it can be seen from the schematic above

18、 the circuit uses only one compare, two additions and several increments to be executed for each coordinate pair determination. 3 Designing using Amplitude Centered DDFS ArchitectureTuning the architecture to best suit a particular application is an important step in the design process. Variants of

19、both the algorithm and the particular implementation must be coordinated to fit the requirements of the application.Before committing to a HDL description for synthesis a PicoBlaze emulation of the generator is proposed to be used to determine a set of initial instantiations of the main components.

20、This key design choices are determined by the design engineeras best suited to the application and become synthesis constrains. The PicoBlaze processor from Xilinx was chosen as a digital generator emulator medium for samples tracking during generation. Variables for output timing as well as multipl

21、exing and buffering requirements can be easily followed with accuracy and more insight. The PicoBlaze architecture is of the same order of complexity as the amplitude based digital synthesizer module and the flexibility to add extensions makesthe PicoBlaze a good choice as an emulator nucleus of the

22、 digital synthesizer development framework. The use of the PicoBlaze in digital synthesis projectsis also well supported and encouraged by Xilinx 12. Additional loading, modulation and mirroring circuits, specific to different applications can also be emulated and validated in the same environment.3

23、.1 Amplitude, Frequency and Phase Tuning of the Amplitude Centered ArchitectureThe main advantage of the amplitude based DDFS architecture is the much reduced circuit resources requirement. Also the circuit gate count is linear in amplitude precision word length not exponential like in the case of c

24、lassical architectures. Frequency tuning must be loaded at cycle start as an input digital variable. The very accurate and versatile FSK capacity of DDFS architectures is preserved. The quadrate output inherent to DDFS architectures is retained in the new amplitude based architectures since the hard

25、ware implementation of the algorithm generates both sine and cosine.2.2 Spectral Purity and Maximum Frequency of the Generated SignalsThe spectral purity characteristic of the generated signals is very important for successful application of the architecture in practice.Fig. 3. Estimated power spect

26、rum of the signal with amplitude algorithm and timing compensation.High quality signals can be generated with the extended algorithm that includes phase timing compensation. The FFT analysis of the generated signals using theOriginal algorithm reveals a spectrum with first odd harmonics are a factor

27、 of about -35 dB below the central frequency. Signal of even lower harmonics content can be.Obtained using more elaborate phase timing compensation methods. Phase truncation before conversion to amplitude is not necessary in the amplitude based architecture and the problem of spur frequencies thus g

28、enerated in the output is eliminated. The upper frequency limit is given by the maximum clock frequency available in the target technology scaled down by the phase compensation counters length. As a result the maximum frequency of the generated signal is reduced accordingly. In order to increase the

29、 maximum frequency of the generated signal timing delay truncation is one option.Fig. 4. Sample truncated timing in order to increase the maxim possible frequency of the generated signal. The effect of sample delay timing truncation is a increase in the output noise similar to quantization noise.4 P

30、icoBlaze Emulator and Extensions for Solution Tuning ahead of Synthesis The PicoBlaze microcontroller was designed aiming the objectives of simplicity and low deployment cost. Typical implementations in a FPGA together with a block RAM that stores the instructions can be simulated in the performant

31、Xilinx ISE environment and its states easily tracked. The PicoBlaze is supported by development tools including an assembler, an integrated development environment (ISE) and a third party graphical instruction set simulator software tool. Furthermore, the PicoBlaze microcontroller is provided as a f

32、ree, source-level VHDL file with royalty-free reuse within Xilinx FPGA thus avoiding proprietary issues. Fig. 5 Outline of the PicoBlaze code development environment for direct digital synthesis moduleFor the purpose of this project the Mediatronix pBlaze IDE assembler and graphical instruction set

33、simulator was used.Fig.6. Example of a complete module in a multiple frequency synthesis application The DDFS module was implemented in assembly code using byte-wide arithmetic. The 16 byte-wide general-purpose data registers are just sufficient to accommodate the variables for two frequency synthes

34、izer module simultaneously.The basic amplitude generation module was implemented in PicoBlaze assembly code in both original eight bit wide world length and a extended double byte version.The timing function was implemented in a hardware module as add on to the core PicoBlaze emulated module 12.Tabl

35、e 1The results of the ICE synthesis of the emulated module and its timing circuit are presented in Table 1 Gate count is very low and nearly equal to the gate count synthesis result for an amplitude based DDFS architecture of the manually instantiated reference.5 Sample DDFS Design Project ResultsEv

36、ery synthesized frequency application has its specific needs that are difficult to define in the early stages of the design. The project in this example is an ongoing project in the field of Electrical Bio- Impedance hardware development. The objective of the project is to design a flexible and tuna

37、ble three frequency generators for use in the MIT tomography 9. The amplitude based DDFS architecture as proposed was found as well suited for compact generator implementation placed next to each magnetic field generator coil. The design target device for the final implementation is the Xilinx Spart

38、an 3 series. The master timing can be implemented by division of master clock frequency using the DCM (Digital Clock Manager) module 10. Direct implementation in VHDL of a flexible clock scheme using the capabilities the Xilinx DCM (Digital Clock Manager) would be difficult to accomplish. The PicoBl

39、aze Digital Synthesizer Emulation Environment was used to explore the solutions to generate simultaneously three frequencies using for each a direct frequency synthesizer module and clock obtained from a associated DCM resource. One simple solution identified was to generate the three frequencies sc

40、aled in amplitude using the same clock frequency and stabilized for jitter by the DCM. The leveling of amplitudes is done by truncating the two least significant bits.Fig.7 PicoBlaze simulation of multi frequency signal generated using the amplitude based DDFS architecture6 ConclusionsThe paper pres

41、ents a design framework for frequency synthesis using the amplitude based DDFS architecture targeting FPGA implementation. In depthAnalysis of the algorithm outlines the timing method and the output frequency spectrum of the generated signal. This was found as on of the main qualities ofThe proposed

42、 architecture with great practical importance. A development framework is exemplified for design insight and internal variable visibility using theXilinx ISE environment and a PicoBlaze software emulation for the amplitude generating module. Emulation in assembly code of the amplitude generator modu

43、le and the synthesis results for Xilinx Spartan 3 family of devices proved the majorAdvantage of the amplitude based architecture the flexibility to implement multi frequency signal generation with a very low gate count. A practical application sample design space exploration and solution proofing i

44、s also presented.Further work is necessary to determine the highest signal frequency by timing delay truncation.References1 I. Jivet B. Dragoi Direct Digital Synthesizer Architecture based on Amplitude Sequencing, Proceedings of the 9th Intrenational WSEAS Conference on Circuits, Crete, July 07, p. 421-4252 B.W. Jordan, W.J. Lennon, and B.D Holm. An Impro