外文翻譯《80C518位 單片機(jī)系列》

1、 本科畢業(yè)設(shè)計(jì)（外文翻譯）80c51 8-bit microcontroller family80c51 8位 單片機(jī)系列 第 15 頁(yè) 80c51 8-bit microcontroller familydescription the philips 8xc51/31 is a high-performance static 80c51 design fabricated with philips high-density cmos technology with operation from 2.7v to 5.5v.the 8xc51/31 contains a 4k 8 rom, a

2、128 8 ram, 32 i/o lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial i/o port for either multi-processor communications, i/o expansion or full duplex uart, and on-chip oscillator and clock circuits.in addition, the device is a low power static

3、design which offers a wide range of operating frequencies down to zero. two software selectable modes of power reduction idle mode and power-dow mode are available. the idle mode freezes the cpu while allowing the ram, timers, serial port, and interrupt system to continue functioning. the power-down

4、 mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped.features（1）8051 central processing unit-4k 8

5、 rom (80c51)-128 8 ram-three 16-bit counter/timers-full duplex serial channel-boolean processor-full static operation-low voltage (2.7v to 5.5v 16mhz) operation（2）memory addressing capability-64k rom and 64k ram（3）power control modes:-clock can be stopped and resumed-idle mode-power-down mode（4）cmos

6、 and ttl compatible（5）three speed ranges at vcc = 5v-0 to 16mhz-0 to 33mhz（6）three package styles（7）extended temperature ranges（8）dual data pointers（9）second dptr register（10）security bits:-rom (2 bits)-otp/eprom (3 bits)（11）encryption array -64 byte（12）4 level priority interrupt（13）6 interrupt sour

7、ces（14）four 8-bit i/o ports（15）full -duplex enhanced uart-framing error detection-automatic address recognition（16）programmable clock out（17）asynchronous port reset（18）low emi (inhibit ale)（19）wake-up from power down by an external interrupt (8xc51)pin configurationsfigure 1 pin configurationspin de

8、scriptionsvss (20): ground: 0v reference.vcc (40): power supply: this is the power supply voltage for normal, idle, and power-down operation.p0.0p0.7 (39-32): port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inp

9、uts. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. port 0 also outputs the code bytes during program verification and received code bytes during eprom programm

10、ing. external pull-ups are required during program verification.p1.0p1.7 (1-8): port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are exter

11、nally pulled low will source current because of the internal pull-ups. port 1 also receives the low-order address byte il during program memory verification. alternate functions for port 1 include:t2 (p1.0): timer/counter 2 external count input/clock out.t2ex (p1.1): timer/counter 2 reload/capture/d

12、irection control.p2.0p2.7 (21-28): port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current be

13、cause of the internal pull-ups. port 2 emits the high-order address byte il during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (movx dptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to exter

14、nal data memory that uses 8-bit addresses (mov ri), port 2 emits the contents of the p2 special function register. some port 2 pins receive the high order address bits during eprom programming and verification.p3.0p3.7 (10-17): port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups

15、. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. port 3 also serves the special features of the 80c51 il family, as listed below:rxd

16、(p3.0): serial input porttxd (p3.1): serial output portint0 (p3.2): external interruptint1 (p3.3): external interruptt0 (p3.4): timer 0 external inputt1 (p3.5): timer 1 external inputwr (p3.6): external data memory writes stroberd (p3.7): external data memory read stroberst (9): reset: a high on thi

17、s pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to vss permits a power-on reset using only an external capacitor to vcc.ale/prog (30): address latch enable/program pulse: output pulse for latching the low byte of the address during an ac

18、cess to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog) during epro

19、m programming. ale can be disabled by setting sfr auxiliary 0. with this bit set, ale will be active only during a movx instruction.psen (29): program store enable: the read strobe to external program memory. when the 8xc51/31 is executing code from the external program memory, psen is activated twi

20、ce each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory.ea/vpp (31): external access enable/programming supply voltage: ea must beexternally held lo to enable the device to fetch

21、 code from external program memory locations 0000h and 0fffh. if ea is held high, the deviceexecutes from internal program memory unless the program counter contains an address greater than 0fffh. this pin also receives the 12.75v programming supply voltage (vpp) during eprom programming. if securit

22、y bit 1 is programmed, ea will be internally latched on reset.xtal1 (19): crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits.xtal2 (18): crystal 2: output from the inverting oscillator amplifier.to avoid“l(fā)atch-up”effect at power-on, the voltage

23、on any pin at any time must not behigher than vcc +0.5v or vss -0.5v, respectively.oscillator characteristicsxtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator, as shown in the logic symbol.to drive the devic

24、e from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times s

25、pecified in the data sheet must be observed.reseta reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. to insure a good power-up reset, the rst pin must be high long enough to allow the oscillator time to start u

26、p (normally a few milliseconds) plus two machine cycles.stop clock modethe static design enables the clock speed to be reduced down to 0 mhz (stopped). when the oscillator is stopped, the ram and special function registers retain their values. this mode allows step-by-step utilization and permits re

27、duced system power consumption by lowering the clock frequency down to any value. for lowest power consumption the power down mode is suggested.idle modein idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last in

28、struction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at t

29、he interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.power-down modeto save even more power, a power down mode can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power d

30、own is the last instruction executed. the on-chip ram and special function registers retain their values down to 2.0v and care must be taken to return v cc to the minimum specified operating voltages before the power down mode is terminated.for the 87c51 and 80c51 either a hardware reset or external

31、 interrupt can be used to exit from power down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. wupd (auxr1.3cwakeup from power down) enables or disables the wakeup from power down with external

32、interrupt.where:wupd = 0 disablewupd = 1 enableto properly terminate power down the reset or external interrupt should not be executed before vcc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). with

33、an external interrupt, int0 or int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instructi

34、on that put the device into power down. for the 80c31, wakeup from power down is always enabled.lpepthe eprom array contains some analog circuits that are not required when vcc is less than 4v, but are required for a vcc greater than 4v. the lpep bit (auxr.4), when set, will power down these analog

35、circuits resulting in a reduced supply current. this bit should be set only for applications that operate at a vcc less than 4v.design considerationwhen the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles be

36、fore the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle sho

37、uld not be one that writes to a port pin or to external memory.once modethe once (on-circuit emulation) mode facilitates testing a debugging of systems without the device having to be removed from the circuit. the once mode is invoked by:1. pull ale low while the device is in reset and psen is high;

38、2. hold ale low as rst is deactivated.while the device is in once mode, the port 0 pins go into a float are weakly pulled state, and the other port pins and ale and psen high. the oscillator circuit remains active. while the 8xc51/31 is in this mode, an emulator or test cpu can be used to drive the

39、circuit. normal operation is restored when a normal reset is applied.programmable clock-outa 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed:1. to input the external clock for timer/counter 2, or

40、2. to output a 50% duty cycle clock ranging from 61hz to 4mhz at a 16mhz operating frequency.to configure the timer/counter 2 as a clock generator, bit c/t2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency de

41、pends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation:where:(rcap2h, rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer.in the clock-out mode timer 2 roll-overs will not generate an interrupt. this is

42、 similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simultaneously. note, however, that the baud-rate and the clock-out frequency will be the same.timer 2timer 2 is a 16-bit timer/counter which can operate as either an ev

43、ent timer or an event counter, as selected by c/t 2* in the special function register t2con. timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator, which are selected by bits in the t2con as shown in table.table1 timer 2 operating modesrclk + tclk cp/

44、rl2tr2mode00116-bit auto-reload 0 1 116-bit capture 1 x 1baud rate generator x x 0(off)capture modein the capture mode there are two options which are selected by bit exen2 in t2con. if exen2=0, then timer 2 is a 16-bit timer or counter (as selected by c/t2* in t2con) which, upon overflowing sets bi

45、t tf2, the timer 2 overflow bit. this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2= 1, timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input t2ex causes the current value in the ti

46、mer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 overflow interrupt. the timer 2 interrupt se

47、rvice routine can interrogate tf2 and exf2 to determine which event caused the interrupt). there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2ex pin transitions or osc/12 pulses.auto-reload mode (up or down counter)in th

48、e 16-bit auto-reload mode, timer 2 can be configured (as either a timer or counter (c/t2* in t2con) then programmed to count up or down. the counting direction is determined by bit dcen (down counter enable) which is located in the t2mod register. when reset is applied the dcen=0 which means timer 2

49、 will default to counting up. if dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin.baud rate generator modebits tclk and/or rclk in t2con allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk= 0, timer 1 is us

50、ed as the serial port transmit baud rate generator. when tclk= 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates -one generated by

51、 timer 1, the other by timer 2.usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). as a baud rate generator, it increments every state time (i.e., 1/2 the oscillator frequency). thus the baud rate formula is as follows:where: (rcap2h, rcap2l) = the conte

52、nt of rcap2h and rcap2l taken as a 16-bit unsigned integer.summary of baud rate equationstimer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2 (p1.0) the baud rate is:if timer 2 is being clocked internally, the baud rate is:where f osc = oscillator frequencyto obtain th

53、e reload value for rcap2h and rcap2l, the above equation can be rewritten as:80c51 8位 單片機(jī)系列概述philips p87c51 是由philips 高密度cmos 工藝制造的高性能單片機(jī)。操作電壓為2.7v至5.5v。p87c51 單片機(jī)有4k 字節(jié)otp rom，128 字節(jié)ram，4 個(gè)8 位i/o 口，三個(gè)16 位定時(shí)/計(jì)數(shù)器，六個(gè)中斷源，4個(gè)中斷優(yōu)先級(jí)的可嵌套中斷結(jié)構(gòu)，一個(gè)串行i/o 口用于多處理器通信或全雙工uart，在片振蕩時(shí)鐘電路。另外，p87c51 單片機(jī)進(jìn)行了低功耗靜態(tài)設(shè)計(jì)，能在寬范圍的操

54、作頻率下工作，甚至0hz。減少功耗的模式可通過(guò)軟件選擇空閑模式和掉電模式。空閑模式凍結(jié)cpu，而允許ram、定時(shí)器、串行口和中斷系統(tǒng)繼續(xù)工作。掉電模式可保存ram 的內(nèi)容，但凍結(jié)了振蕩器，以致所有其它片內(nèi)功能都被禁止。設(shè)計(jì)了靜態(tài)操作模式，在不丟失用戶(hù)數(shù)據(jù)的情況下，時(shí)鐘可停止工作，也可從時(shí)鐘停止處恢復(fù)執(zhí)行程序。特性(1)8051 中央處理單元4k8 otp rom1288 ram三個(gè)16 位定時(shí)/計(jì)數(shù)器全雙工串行通道布爾處理全靜態(tài)操作低電壓操作（2.7v5.5v）(2)貯存器尋址能力64k rom 和64k ram(3)電源控制模式：時(shí)鐘的停止和恢復(fù)空閑模式掉電模式(4)兼容cmos 和ttl(

55、5)在5v 時(shí)的頻率范圍016mhz033mhz(6)三種封裝形式(7)可擴(kuò)展的溫度范圍(8)雙數(shù)據(jù)指針(9)兩個(gè)dptr 寄存器(10)保密位:otp rom（3 位）(11)加密矩陣64 字節(jié)(12)4個(gè)中斷優(yōu)先級(jí)(13)六個(gè)中斷源(14)四個(gè)八位i/o 口(15)全雙工增強(qiáng)型uart幀數(shù)據(jù)錯(cuò)誤檢測(cè)自動(dòng)地址識(shí)別(16)可編程時(shí)鐘輸出(17)異步端口復(fù)位(18)低emi（禁止ale）(19)外部中斷能喚醒掉電模式pdip 封裝及管腳功能圖1 針腳配置管腳描述vss (20): 接地: 0v為標(biāo)準(zhǔn)vcc (40): 電源: 提供掉電、空閑、正常電壓p0.0p0.7 (39-32): p0口:p

56、0口是開(kāi)漏雙向i/o 口,可以寫(xiě)1 用作高阻抗懸浮，也當(dāng)訪問(wèn)外部程序和數(shù)據(jù)存儲(chǔ)器時(shí)，p0 口分時(shí)輸出外部存貯器的低8 位地址和傳送數(shù)據(jù)信息，當(dāng)發(fā)送1,p0口采用內(nèi)部強(qiáng)上拉p1.0p1.7 (1-8): p1口:p1口是帶內(nèi)部上拉的雙向i/o 口,向p1口寫(xiě)1時(shí),p1口被內(nèi)部上拉為高電平，并且可以用作輸入口。當(dāng)作為輸入時(shí),p1 口管腳被外部拉低，因?yàn)閮?nèi)部上拉而產(chǎn)生電流。在程序存貯器校驗(yàn)時(shí)，p1 口也可接收低8位地址。p1 口還可用作如下特殊功能：t2(p1.0):定時(shí)器/計(jì)數(shù)器2 的外部計(jì)數(shù)輸入/時(shí)鐘輸出t2ex(p1.1): 定時(shí)器/計(jì)數(shù)器2 重裝載/捕捉/方向控制p2.0p2.7 (21-2

57、8): p2口是帶內(nèi)部上拉的8 位雙向i/o 口，向p2口寫(xiě)1 時(shí)，p2口被內(nèi)部上拉為高電平，并且用作輸入口。作為輸入口時(shí)，p2口管腳被外部拉低，因?yàn)閮?nèi)部上拉而產(chǎn)生電流。在訪問(wèn)外部數(shù)據(jù)存貯器時(shí)，p2口發(fā)送16 位地址的高字節(jié)(movx dptr)，利用8 位尋址方式(mov ri)，p2口向外部數(shù)據(jù)存貯器發(fā)送p2 特殊功能寄存器的內(nèi)容。在eprom編程和確認(rèn)過(guò)程中，p2 口管腳接收高字節(jié)地址p3.0p3.7 (10-17): p3口是帶內(nèi)部上拉的8 位雙向i/o 口，向p3口寫(xiě)1 時(shí)，p3口被內(nèi)部上拉為高電平，并且用作輸入口，作為輸入口時(shí)，p3 管腳被外部拉低，因?yàn)閮?nèi)部上拉而產(chǎn)生電流。p3 口還可用作如下特殊功能:rxd(p3.0): 串行輸入口txd(p3.1): 串行輸出口int0(p3.2): 外部中斷0int1(p3.3): 外部中斷1t0(p3.4): 定時(shí)器0 外部輸入t1(p3.5): 定時(shí)器1 外部輸入wr(p3.6): 外部數(shù)據(jù)存儲(chǔ)器寫(xiě)信號(hào)rd(p3.7): 外部數(shù)據(jù)存儲(chǔ)器讀信號(hào)rst (9): 當(dāng)晶振在運(yùn)行,只要復(fù)位管腳出現(xiàn)2個(gè)機(jī)器周期高電平即