實驗九 硬件樂曲自動演奏電路設(shè)計.doc

驗十 硬件樂曲自動演奏電路設(shè)計1、 實驗?zāi)康模簩W(xué)習(xí)利用數(shù)控分頻器設(shè)計硬件電子琴實驗。2、 實驗儀器：PC機，操作系統(tǒng)為Windows2000/xp, Quartus II 5.1 設(shè)計平臺，GW48系列SOPE/EDA實驗開發(fā)系統(tǒng)。3、 實驗原理：本設(shè)計樂曲選取梁祝中化蝶部分，其簡譜如圖1所示。圖1 梁祝中化蝶部分簡譜組成樂曲的每個音符的發(fā)音頻率值及其持續(xù)的時間是樂曲能連續(xù)演奏所需的2個基本要素，首先讓我們來了解音符與頻率的關(guān)系。樂曲的12平均率規(guī)定：每2個八度音(如簡譜中的中音1與高音1)之間的頻率相差1倍。在2個八度音之間，又可分為12個半音，每2個半音的頻率比為。另外，音符A(簡譜中的低音6)的頻率為440Hz，音符B到C之間、E到F之間為半音，其余為全音。由此可以計算出簡譜中從低音1至高音1之間每個音符的頻率，如表1所示。表1 簡譜中音符與頻率的關(guān)系4、 主系統(tǒng)由4個模塊組成；例1-1是頂層設(shè)計文件，其內(nèi)部有三個功能模塊（如圖2所示）：Tone.VHD(例1-2)和Speaker.VHD（例1-3）及Notetabs.VHD（例1-4）.模塊TONE是音階發(fā)生器，當(dāng)4位發(fā)聲控制輸入INDEX中某一位為高電平時，則對應(yīng)某一音階的數(shù)值將從端口TONE輸出，作為獲得該音階的分頻預(yù)置值；同時由CODE輸出對應(yīng)該音階簡譜的顯示數(shù)碼，如5，并由HIGH輸出指示音階高8度顯示。由例6-28可見，其語句結(jié)構(gòu)只是類似與真值表的純組合電路描述，其中的音階分頻預(yù)置值，如Tone Indx, Tone=Tone2,CODE=CODE1,HIGH=HIGH1);u2 : Speaker PORT MAP (clk=CLK12MHZ,Tone1=Tone2, SpkS=SPKOUT );u3 : Notetabs PORT MAP(clk=CLK8HZ,Index0=Indx);END;【例10-2】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Tone IS PORT ( Index : IN INTEGER RANGE 0 TO 15; CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC; Tone : OUT INTEGER RANGE 0 TO 16#7FF# );END;ARCHITECTURE one OF Tone ISBEGIN Search : PROCESS(Index) BEGIN CASE Index IS - 譯碼電路，查表方式，控制音調(diào)的預(yù)置數(shù) WHEN 0=Tone = 2047; CODE = 0; HIGH Tone = 773; CODE = 1; HIGH Tone = 912; CODE = 2; HIGH Tone = 1036; CODE = 3; HIGH Tone = 1197; CODE = 5; HIGH Tone = 1290; CODE = 6; HIGH Tone = 1372; CODE = 7; HIGH Tone = 1410; CODE = 1; HIGH Tone = 1480; CODE = 2; HIGH Tone = 1542; CODE = 3; HIGH Tone = 1622; CODE = 5; HIGH Tone =1668; CODE = 6; HIGH Tone = 1728; CODE = 1; HIGH NULL; END CASE; END PROCESS;END;【例10-3】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Speaker IS PORT ( clk : IN STD_LOGIC; Tone1 : IN INTEGER RANGE 0 TO 16#7FF#; SpkS : OUT STD_LOGIC );END;ARCHITECTURE one OF Speaker IS SIGNAL PreCLK , FullSpkS : STD_LOGIC; BEGIN DivideCLK : PROCESS(clk) - 將CLK進 11分頻，PreCLK為C L 11K 6分頻 VARIABLE Count4 : INTEGER RANGE 0 TO 15; BEGIN PreCLK 11 THEN PreCLK = 1; Count4 := 0; ELSIF clkEVENT AND clk=1 THEN Count4 := Count4 + 1; END IF; END PROCESS; GenSpkS : PROCESS(PreCLK, Tone1) VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#; BEGIN - 11位可預(yù)置計數(shù)器 IF PreCLKEVENT AND PreCLK = 1 THEN IF Count11=16#7FF# THEN Count11 := Tone1; FullSpkS = 1; ELSE Count11:=Count11 + 1; FullSpkS = 0; END IF; END IF; END PROCESS; DelaySpkS : PROCESS(FullSpkS) VARIABLE Count2 : STD_LOGIC; BEGIN IF FullSpkSEVENT AND FullSpkS = 1 THEN Count2 := NOT Count2; IF Count2 = 1 THEN SpkS = 1; ELSE SpkS = 0; END IF; END IF; END PROCESS;END;【例10-4】library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Notetabs isPort ( clk: in std_logic; -系統(tǒng)時鐘；鍵盤輸入/自動演奏 index0 : out INTEGER RANGE 0 TO 15); -音符信號輸出end NOTETABS;architecture Behavioral of Notetabs issignal count0:integer range 0 to 138;-changebeginmusic:process(clk) -此進程完成自動演奏部分曲的地址累加beginif clkevent and clk=1 thenif count0=138 then count0=0;else count0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0inde