數(shù)字系統(tǒng)仿真與VHDL課程設(shè)計(jì)報(bào)告.doc

數(shù)字系統(tǒng)仿真與VHDL課程設(shè)計(jì)報(bào)告學(xué)院：信息與電氣工程學(xué)院專業(yè)：通信工程班級(jí)：通信一班姓名：李世輝學(xué)號(hào)：0804040102指導(dǎo)老師：張劍 胡仕剛設(shè)計(jì)時(shí)間：2010.1.32010.1.14 目錄1 課程設(shè)計(jì)任務(wù)2 課程設(shè)計(jì)目的3 課程設(shè)計(jì)的基本要求4 設(shè)計(jì)流程圖5 Max+plus II設(shè)計(jì)軟件的基本操作6 課程設(shè)計(jì)內(nèi)容七課程設(shè)計(jì)心得體會(huì)一課程設(shè)計(jì)的任務(wù)1.本次設(shè)計(jì)的任務(wù)是熟悉支持VHDL語(yǔ)言的軟件，例如：MAXPLUS2，ISP，F(xiàn)OUNDATION等，利用這一類軟件使用VHDL語(yǔ)言進(jìn)行設(shè)計(jì)。二課程設(shè)計(jì)目的1. 熟練掌握相關(guān)軟件的使用，操作。能對(duì)VHDL語(yǔ)言程序進(jìn)行編譯，調(diào)試，以及通過(guò)計(jì)算機(jī)仿真，得到正確的仿真波形圖，并根據(jù)所得仿真波形圖分析判斷并改進(jìn)所設(shè)計(jì)的電路。2. 在成功掌握軟件操作基礎(chǔ)上，將所學(xué)數(shù)字電路的基礎(chǔ)課知識(shí)與VHDL語(yǔ)言的應(yīng)用型知識(shí)結(jié)合起來(lái)并與實(shí)際設(shè)計(jì)，操作聯(lián)系起來(lái)，即“理論聯(lián)系實(shí)際”。3. 深入了解VHDL語(yǔ)言的作用與價(jià)值，對(duì)用硬件語(yǔ)言設(shè)計(jì)一個(gè)電路系統(tǒng)開(kāi)始具備一個(gè)較完整的思路與較專業(yè)的經(jīng)驗(yàn)。對(duì)EDA技術(shù)有初步的認(rèn)識(shí)，并開(kāi)始對(duì)EDA技術(shù)的開(kāi)發(fā)創(chuàng)新有初步的理解。三設(shè)計(jì)的基本要求 1.熟悉數(shù)字電路及相關(guān)專業(yè)課程的基本知識(shí)并能聯(lián)系具體程序 2.正確操作使用VHDL語(yǔ)言相關(guān)軟件，能編譯，調(diào)試，仿真VHDL 語(yǔ)言程序 3.設(shè)計(jì)數(shù)字電路，編寫程序，實(shí)現(xiàn)電路功能。四. 設(shè)計(jì)流程圖 五Max+plus II設(shè)計(jì)軟件的基本操作 1.設(shè)計(jì)輸入 原理圖設(shè)計(jì)輸入法 文本設(shè)計(jì)輸入法 波形輸入法 層次化設(shè)計(jì)輸入法 2.項(xiàng)目編譯 語(yǔ)法檢查和設(shè)計(jì)規(guī)則檢查 設(shè)計(jì)綜合 生成編程數(shù)據(jù)文件 3.仿真和定時(shí)分析 仿真(Simulation) 定時(shí)分析(Timing Analysis) 4.編程下載，調(diào)試與仿真 5.波形圖的分析六課程設(shè)計(jì)內(nèi)容 1.設(shè)計(jì)60進(jìn)計(jì)數(shù)器設(shè)計(jì)一個(gè)BCD碼60進(jìn)計(jì)數(shù)器。要求實(shí)現(xiàn)同步，異步兩種情況，且規(guī)定個(gè)位顯示09，十位顯示05，均用4位二進(jìn)制數(shù)表示。在此基礎(chǔ)上試用VHDL語(yǔ)言描述中小規(guī)模集成電路74LS169。(1) .60進(jìn)制同步計(jì)數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count60tb ISPORT(clk,w1c,w2c,cin:IN STD_LOGIC; cout:OUT STD_LOGIC; data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ge:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); shi:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY count60tb;ARCHITECTURE example OF count60tb ISSIGNAL ge_n:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL shi_n:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINge=ge_n;shi=shi_n;PROCESS(clk,w1c) ISBEGINIF(W1C=1) THENge_n=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin=1) THEN IF(ge_n=9) THENge_n=0000;ELSEge_n=ge_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(clk,w2c) ISBEGINIF(w2c=1) THENshi_n=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin=1 AND ge_n=9) THENIF(shi_n=5) THENshi_n=0000;ELSEshi_n=shi_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ge_n,shi_n) ISBEGINIF(clkEVENT AND clk=1 )THENIF(ge_n=9 AND shi_n=5 AND cin=1) THENcout=1;ELSEcout=0;END IF;END IF;END PROCESS;END ARCHITECTURE example;(2) 60進(jìn)制異步計(jì)數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count60yb ISPORT(clk,w1c,w2c,cin1:IN STD_LOGIC; cout2:OUT STD_LOGIC; data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ge:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); shi:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY count60yb;ARCHITECTURE example OF count60yb ISSIGNAL ge_n:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL shi_n:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL cin2,cout1:STD_LOGIC;BEGINge=ge_n;shi=shi_n;cin2=cout1;PROCESS(clk,w1c) ISBEGINIF(W1C=1) THENge_n=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin1=1) THEN IF(ge_n=9) THENge_n=0000;ELSEge_n=ge_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(cin2) ISBEGINIF(w2c=1) THENshi_n=data_in(3 DOWNTO 0);ELSEIF(cin2=1) THENIF(shi_n=5) THENshi_n=0000;ELSEshi_n=shi_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ge_n,shi_n) ISBEGINIF(clkEVENT AND clk=1 )THENIF(ge_n=9 AND cin1=1) THENcout1=1;ELSEcout1=0;END IF;IF(shi_n=5 AND cin2=1) THENcout2=1;ELSEcout2=0;END IF;END IF;END PROCESS;END ARCHITECTURE example;(3) 74LS169模塊LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ls169 ISPORT(clk,wr,sel,cin:IN STD_LOGIC; cout:OUT STD_LOGIC; data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0);data_out:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY ls169;ARCHITECTURE example OF ls169 ISSIGNAL data:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINdata_out=data;PROCESS(clk,wr) ISBEGINIF(wr=1) THENdata=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin=1) THEN IF(sel=1)THEN IF(data=15) THENdata=0000;cout=1;ELSEdata=data+1;cout=0;END IF;ELSE IF(data=0000) THENdata=1111;cout=1;ELSEdata=data-1;cout=0;END IF;END IF;END IF;END IF;END PROCESS;END ARCHITECTURE example;2.循環(huán)彩燈控制器設(shè)計(jì)一個(gè)循環(huán)彩燈控制器，該控制器控制紅，綠，黃三個(gè)發(fā)光管循環(huán)點(diǎn)亮。要求紅發(fā)光管亮3秒，綠發(fā)光管亮2秒，黃發(fā)光管亮1秒。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY xhcaideng ISPORT(clk,clr:IN STD_LOGIC;red,green,yellow:OUT STD_LOGIC);END ENTITY xhcaideng;ARCHITECTURE example OF xhcaideng ISSIGNAL dout:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL m:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINred=dout(2);green=dout(1);yellow=dout(0);PROCESS(clk) ISBEGINIF(clr=1) THENm=001;ELSIF(clkEVENT AND clk=1) THENIF(m=110) THENm=001;ELSEmdoutdoutdoutdoutdoutdoutdout=111;END CASE;END IF;END PROCESS;END ARCHITECTURE;3.數(shù)字顯示的秒表設(shè)計(jì)一塊用數(shù)碼管顯示的秒表，能夠準(zhǔn)確的計(jì)時(shí)并顯示。最大計(jì)時(shí)為59秒，最小精確到0.1秒。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity miaobiao isport(clk:in std_logic;din:in std_logic_vector(3 downto 0);wr3,wr2,wr1:in std_logic;dout3:out std_logic_vector(3 downto 0);dout2:out std_logic_vector(3 downto 0);dout1:out std_logic_vector(3 downto 0);end entity miaobiao;architecture example of miaobiao issignal out3: std_logic_vector(3 downto 0);signal out2: std_logic_vector(3 downto 0);signal out1: std_logic_vector(3 downto 0);begindout3=out3;dout2=out2;dout1=out1;process(clk) isbeginif(clkevent and clk=1) thenif(wr1=1) thenout1=din;elsif(out1=1001) thenout1=0000;elseout1=out1+1;end if;end if;end process;process(clk) isbeginif(clkevent and clk=1) thenif(wr2=1) thenout2=din;elsif(out1=1001) then if(out2=1001) thenout2=0000;else out2=out2+1;end if;end if;end if;end process;process(clk) isbeginif(clkevent and clk=1) thenif(wr3=1) thenout3=din;elsif(out1=1001) thenif(out2=1001) thenif(out3=0101) thenout3=0000;else out3=out3+1;end if;end if;end if;end if;end process;end architecture example;4.設(shè)計(jì)一個(gè)2人搶答器兩人搶答，先搶為有效，用發(fā)光二極管顯示是否搶到優(yōu)先答題權(quán)。答題結(jié)束后，按復(fù)位鍵可重新?lián)尨鹣乱活}。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity answer2 isport(reset:in std_logic;player:in std_logic_vector(2 downto 1);out1:out std_logic;out2:out std_logic;fail:out std_logic);end entity answer2;architecture example of answer2 issignal a:std_logic_vector(2 downto 0);beginout2=a(2);out1=a(1);fail=a(0);process(reset,player) isbeginif(reset=0) thenaaaaa=001;end case;end if;end process;end architecture example;5.交通燈控制器的程序設(shè)計(jì)對(duì)所提供的交通燈實(shí)驗(yàn)程序進(jìn)行改寫，原來(lái)為兩個(gè)相位的交通控制轉(zhuǎn)變?yōu)樗膫€(gè)相位，即：東西直行，東西左轉(zhuǎn)，南北直行，南北左轉(zhuǎn)，加入一個(gè)方向顯示燈的控制。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jiaotongdeng isport(R1,G1,Y1,L1:out std_logic;R2,G2,Y2,L2:out std_logic;clk:in std_logic);end entity jiaotongdeng;architecture example of jiaotongdeng issignal m:std_logic_vector(6 downto 0):=0000000;signal n:std_logic_vector(6 downto 0):=0000000;signal a:std_logic_vector(3 downto 0);signal b:std_logic_vector(3 downto 0);beginR1=a(3);G1=a(2);Y1=a(1);L1=a(0);R2=b(3);G2=b(2);Y2=b(1);L2=b(0);AA:process(clk) isbeginif(clkevent and clk=1) thenif(m=1100100) thenm=0000001;elsem=m+1;end if;if(m=50) then a=1000;elsif(m=70) thena=0100;elsif(m=75) thena=0010;elsif(m=95) thena=0001;elsea=0010;end if;end if;end process;BB:process(clk) isbeginif(clkevent and clk=1) thenif(n=1100100) thenn=0000001;elsen=n+1;end if;if(n=20) thenb=0100;elsif(n=25) thenb=0010;elsif(n=45) thenb=0001;elsif(n=50) thenb=0010;elseb=1000;end if;end if;end process;end architecture;6. 具有使能和清零作用的16進(jìn)制計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;entity count16 isport( clk :in std_logic;clear:in std_logic;enable:in std_logic;outy:out integer range 0 to 15;counter:out std_logic);end entity count16;architecture behave of count16 isbeginprocess(clk) variable cnt:integer range 0 to 15;beginif(clkevent and clk=1)thenif clear=0 thencnt:=0;elseif enable=1 thencnt:=cnt+1;end if;end if;end if;outy=cnt;if cnt=15 thencounter=1;elsecounter=0;end if;end process;end behave;7. 16路彩燈控制器library ieee;use ieee.std_logic_1164.all;package state_pack istype state is(qa,qb,qc,qd,qe,qf,qg);end state_pack;library ieee;use ieee.std_logic_1164.all;use work.state_pack.all;entity controll isport(k,s,qc1,qc2,clk:in std_logic;y,k1,k2,k3,k4,k5,k6:out std_logic);end controll;architecture rtl of controll issignal current_state:state:=qa;beginprocessbeginwait until clkevent and clk=1;if s=0 theny=0;elsey=1;end if;if k=0 thenk1=0;k2=0;k3=1;k4=1;k5=1;k6=1;current_statecurrent_state=qb;k1=1;k3if qc1=0thencurrent_state=qb;elsecurrent_state=qc;k1=0;k2if qc2=0thencurrent_state=qc;elsecurrent_state=qd;k4if qc2=0 thencurrent_state=qd;el