移頻鍵控的數(shù)模轉換器Digital-to-Analog Converter for FSK英文.doc

Digital-to-Analog Converter for FSK移頻鍵控的數(shù)模轉換器AbstractThis thesis is one part of an overall task of designing a module for frequency shiftkeying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has aDirect Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differentialcurrent signals are directly fed to a RF (Radio Frequency) unit that generates the UWBRF signal. The focus of this thesis is on DAC while the DDS is developed in VHDL asanother thesis work.This thesis demonstrates a low-power, ultra wide band 10-bit DAC with an updatefrequency of 24 MSPS (Mega Samples Per Second). The DAC uses a L-fold linearinterpolation architecture. It includes a 16-tap voltage controlled delay line and a 10-bitbinary-weighted DAC with a time interleaved structure. The linear interpolationtechnique improves the attenuation of mirror components and also reduces the glitch.This helps to relax the analog filter requirements and sometimes an off chip capacitor isenough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.In this work various DAC architectures are studied. The current-steering DAC is chosendue to its high speed and high resolution. A binary weighted architecture is chosen toreduce the digital circuits. This helped in reducing the power consumption.The design and simulation is done with help of Cadence. The layout is done in CadenceVirtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in130 nm CMOS process.KeywordsDAC, FSK, 10-bit, layout, 130 nm, Digital-To-Analog , CMOS, Common centroidAcknowledgmentsI would like to thank my supervisor Prof. Jiren Yuan, Director of Competence Centrefor Circuit Design, Department of Applied Electronics, Lund University for hisguidance and encouragement. His inspiration and expertise enabled me to complete mythesis successfully. I would like to thank Dr. Peter Valentin Nilsson, AssociateProfessor and Program Manager Socware R&E, Lund University, for his help andguidance. Both of them are very approachable and always ready to clear any doubts.I thank all my teachers in Electronics Systems and Electronic Devices at LinkpingUniversity, especially Prof. Mark Vesterbacka, Prof. Christer Svensson, Prof. AtilaAlvandpour, Prof. Per Lwenborg and Mr. Erik Backenius.Special thanks to my parents for helping me pursue my studies in Sweden. Theirfinancial and emotional support helped me complete my Masters degree successfully.I would like to thank all the loving Swedish people for being such a great andwelcoming hosts for all international students.I am very grateful to my wife Reshma, who supported me throughout my PostGraduation study. I finally dedicate my thesis to my little son Safin.Contents1 Introduction.11.1 Background. 21.3 Organization Of Chapters.32 FSK based Transceiver. 52.1 Introduction. 62.2 Frequency Shift Keying . 62.4 Operation Modes and Control Signals. 93 Digital to Analog Conversion.113.1 Basic Ideal Operation. 124 DAC Architectures. 194.1 Introduction . 204.2 Classifications Of DACs. 204.2.2 Classification Based On Mode Of Operation.204.2.3 Classification Based On Bit Weights.204.2.3 Classification Based On Sampling Frequency. 204.4 Current Source DAC - Thermometer Coded .224.5 Charge Redistribution Switched Capacitor DAC.234.8 Oversampling DACs. 264.9 Linear Interpolation DAC. 264.10 Hybrid Architectures. 265 DAC Figures of Merit.275.1 Introduction . 285.2 Static performance.285.2.1 Quantization Noise . 285.2.2 Offset error and Gain5.3 Dynamic Performance .285.3.1 Settling Time, Rise Time and Fall Time.286 Linear Interpolation DAC. 356.2 Principle of Linear Interpolation. 366.3 L-fold linear interpolation. 386.3.1 Basic Principle.386.4 Architecture.416.5 Glitch In DACs. 426.5.1 Glitch Reduction In Linear Interpolation DACS. 436.7 Unit Current Source . 456.8 Matching And Transistor Sizing. 466.8.3 Selection Of Proper Transistor Size. 466.11.1 RS flip flop. 506.12 Voltage controlled delay. 526.13 Digital Control of Biasing. 537 Layout . 557.1 Introduction. 567.2 Substrate Noise.567.2.1 Inductive Noises (L di /dt).567.2.2 Capacitive Coupling (dv/dt). 577.2.3 Injection Of Minority Carriers. 577.7 Layout . 62. 628.2 Spectrum of 10-bit Normal DAC. 688.2 Performance of 10-bit L-fold DAC.728.3 Conclusions. 72References.75List of FiguresFigure 2.1 FSK modulation .6Figure 2.2 Transceiver block diagram .7Figure 2.3 Overview of the chip.8Figure 3.1 DAC basic function . 12Figure 3.2 Ideally sampled signal .12Figure 3.3 Piecewise constant signal typical of a practical DAC output.13Figure 3.4 Spectrum replication due to sampling.14Figure 3.5 Spectrum replication due to sampling.15Figure 3.6 The sinc function. 16Figure 3.7 Spectrum of the DAC showing both sinc type attenuation as dashed line and idealattenuation as solid line. 17Figure 4.1 Binary weighted current steering DAC.21Figure 4.2 Thermometer coded DAC.22Figure 4.3 Charge Redistribution DAC. 23Figure 4.4 A 4-bit R-2R ladder DAC. 24Figure 4.5 Resistor -String DAC.25Figure 5.1 DAC offset error and gain error. 29Figure 5.2 INL and DNL.30Figure 5.3 The different components of settling Time. 31Figure 5.4 Glitch in DAC.32Figure 5.5 SFDR measurement.33Figure 6.1 Shows impulse response of ZOH and Linear Interpolation. 36Figure 6.2 Frequency response of ZOH and Linear Interpolation function.37Figure 6.3 L-fold linear interpolation.38Figure 6.4 10-bit, 16 tap linear interpolation DAC.40Figure 6.5 DAC output glitch.41Figure 6.6 A section of the L-fold Linear Interpolation Structure.43Figure 6.7 Output current activity during the transition from 0111 - 1000.43Figure 6.8 Current source with switches and isolation transistors. 44Figure 6.9 Allowed deviation of LSB current against expected INL 5. 46Figure 6.10 Switch signal for differential switches. 48Figure 6.11 Driving Stage.50Figure 6.12 D- Latch .51Figure 6.13 D-Latch CMOS implementation.51Figure 6.14 Delay Line. 52Figure 6.15 Current Starved Inverter. 52Figure 6.16 Current Starved Inverter. 53Figure 7.1 Bond Wire and Inductive Injection.56Figure 7.2 A parasitics capacitances in the chip which causes substrate noise.57Figure 7.3 Guard Rings. 58Figure 7.4 Floor Plan of the DAC. 60Figure 7.5 The positions of bit b9 in the transistor array.61Figure 7.6 Layout of Unit Delays and Buffers.62Figure 7.7 Switches and Isolation Transistors. 63Figure 7.8 Driving Stage Layout. 64Figure 7.9 The FSK chip layout.65Figure 8.1 Spectrum of 10-bit normal binary weighted DAC.68Figure 8.2 Spectrum of L-fold DAC.69Figure 8.3 INL of L-fold DAC.70Figure 8.4 DNL of L-fold DAC. 71List of TablesTable 1. Some characteristics for the FSK chip.9Table 2. State of different parameters during transmit and receive mode.9Table 3. Overview of the control signals. 10Table 4. Different DAC Types and corresponding weights. 18Table 5. Performance Summary.721 Introduction11.1 BackgroundData Converters are one of the main fields of research where a lot of effort and time isspent. Why is it so important ? The answer is many of the natural occurring signals areanalog or continuous. Humans can feel only the analog signals. In the modern world ofelectronics most of the signal processing is carried out in the digital domain with 0s and1s. The advantages of digital systems are that they can easily be duplicated and do notdepend on strict component tolerances and system responses do not drift withtemperature. Digital systems are easy to design and have scaled down considerably insize for years. Now billions of transistors are compressed into a small area due to thegrowth of the digital technology.So information has to be converted back and forth into analog and digital modes. Herecomes the importance of Data Converters. Data Converters are of two types. Analog-to-Digital (ADC) and Digital-to-Analog (DAC). ADC converts the naturally occurringsignals to Digital signals and DACs are interfaces between the digital world and analogreal life.Embedded data converters are becoming a new trend where data conversion interfacesalong are integrated along with DSPs (Digital Signal Processing). The trend to putdigital and analog circuits together in a single chip to provide efficient and portablefrequency systems creates new challenges. Main challenges are feasibility of integratingsensitive analog functions in technologies optimized for digital performance, downscaling of supply voltage, spurious signal pick-up from on-chip digital circuitry and lowpower consumption.Much research is going in the field of Data Converters to create low-power, precisedevices like Mobile Phones and Audio/Video devices. The spectral purity of th