(完整版)現(xiàn)代邏輯設(shè)計(jì)英文試卷A-2014

中國(guó)計(jì)量學(xué)院2013~2014學(xué)年第2學(xué)期《現(xiàn)代邏輯設(shè)計(jì)》課程試卷（A）第1頁(yè)共5頁(yè)中國(guó)計(jì)量學(xué)院2013~2014學(xué)年第2學(xué)期《現(xiàn)代邏輯設(shè)計(jì)》課程考試試卷（A）開(kāi)課二級(jí)學(xué)院：信息工程學(xué)院，考試時(shí)間：2014年6月日時(shí)考試形式：閉卷□、開(kāi)卷□，允許帶入場(chǎng)裝訂線考生姓名：學(xué)號(hào)：專(zhuān)業(yè)：裝訂線題序一二三四五六七八九總分得分評(píng)卷人Fillintheblanks.(total20/100,2foreachblank)1、Y=(sel)?(A+B):(A-B);ifthevalueofselis1，theresultofYisA+B,otherwisetheresultofYisA-B.Theoperator“?:”iscalled_條件運(yùn)算符____.2、TheexpandnameofgraphicfileinQuartusIIispdfandtheexpandnameofwaveformfileisvwf.3、Thebinaryformof8’h3fis____8’b00111111_______________.4、Thegeneralsymbolofblockingstatementis=.Thegeneralsymbolofnon-blockingstatementis<=.5、AssumedA=2’b11,B=4’b1001,thevalueof“{A,B}”is___6’b111001_,thevalueof“^b”is___0_____.二、Short-answerquestions.(total20/100)1、InVerilogHDL，what’sthemeaningof“always@(posedgeclk)”and“always@(clk)”?(6/100)第一個(gè)表示在時(shí)鐘上升沿觸發(fā)，第二個(gè)表示在時(shí)鐘高電平觸發(fā)。一個(gè)是邊沿敏感，一個(gè)是電平敏感。2、FiniteStateMachine(FSM)canbedividedintotwotypesaccordingtothegenerationofoutputvalues.What’sthedifferencebetweenthesetwomodels?(6/100)根據(jù)輸出信號(hào)產(chǎn)生方法的不同，狀態(tài)機(jī)可分為兩類(lèi)：mealy和moore。Moore型狀態(tài)機(jī)的輸出僅取決于當(dāng)前狀態(tài)，mealy型狀態(tài)機(jī)的輸出取決于當(dāng)前狀態(tài)和當(dāng)前輸入。3．PleaseexplainthestructureofaVerilogmodulewithexamples.(8/100)四個(gè)部分：模塊申明、端口定義、數(shù)據(jù)類(lèi)型定義、功能描述。Givethedefinitionofthevariablesandconstants.(total12/100,3foreach)Definean8-bitbusofwiretypenamed“ABUS”.wire[7:0]ABUS;Definea16-bitvariableofregtypenamed“address”.reg[15:0]address;裝訂線Defineaparameternamed“delay_time”裝訂線parameterdelay_time=8;Defineamemorywiththewordwidthof32andmemorysizeof128.reg[31:0]memory[127:0];四、Programcomprehension.(total16/100)1、Pleasecorrecttheprogramofan4-bitcomparatorwhichhastwo4-bitinputsaandbandthreeoutputsa_gt_b,a_eq_banda_lt_b.（8/100）module4bit_comp(a,b,a_gt_b,a_eq_b,a_lt_b);input[7:0]a,b;outputa_gt_b,a_eq_b,a_lt_b;rega_gt_b,a_eq_b,a_lt_b;assign a_gt_b=(a>b), a_eq_b=(a=b), a_lt_b=(a<b);endmoduleThisprogramisa3-8decoderwhichhasanenablesignal“en”.When“en”islogic1,thedecoderworksindecodingmode.Fillintheblanks.(8/100)moduledecoder(a,y,en);input[2:0]a;inputen;output[7:0]y__________________;reg[7:0]y__________________;always@(aoren)if(en=1)begincase(a)____________;3’b000:y=8’b11111110;3’b001:y=8’b11111101;3’b010:y=8’b11111011;3’b011:y=8’b11110111;___________11101111;____________;3’b101:y=8’b11011111;3’b110:y=8’b10111111;3’b111:y=8’b01111111;default:y=8’b11111111;endelsey=8’b11111111;endmodule五、Programming(total32/100）1、Accordingtotheschematicdiagram,pleasedesigna2-1MUXinstructuralstyle(usingbuilt-inprimitives).(8/100)modulemux(OUT,A,B,SEL);outputOUT;inputA,B,SEL;notI5(sel_n,SEL);andI6(sel_a,A,SEL);andI7(sel_b,sel_n,B);orI4(OUT,sel_a,sel_b);