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《計(jì)算機(jī)組成實(shí)驗(yàn)C》

課程設(shè)計(jì)

適用專業(yè):電子信息類專業(yè)

專業(yè):

班級:

學(xué)號:

姓名:

指導(dǎo)教師:

實(shí)驗(yàn)學(xué)期:2014-2015第1學(xué)期

西南交通大學(xué)

信息科學(xué)與技術(shù)學(xué)院

簡化計(jì)算機(jī)系統(tǒng)的設(shè)計(jì)

一.實(shí)驗(yàn)?zāi)康模和ㄟ^學(xué)習(xí)簡單的指令系統(tǒng)及其各指令的操作流程,用VHDL語

言實(shí)現(xiàn)簡單的處理器模塊,并通過調(diào)用存儲(chǔ)器模塊,將處理器模塊和存儲(chǔ)器模塊

連接形成簡化的計(jì)算機(jī)系統(tǒng)。

二.實(shí)驗(yàn)內(nèi)容

I.用VHDL語言實(shí)現(xiàn)簡單的處理器模塊。

2.調(diào)用存儲(chǔ)器模塊設(shè)計(jì)256x16的存儲(chǔ)器模塊。

3.將簡單的處理器模塊和存儲(chǔ)器模塊連接形成簡單的計(jì)算機(jī)系統(tǒng)。

4.將指令序列存入存儲(chǔ)器,然后分析指令執(zhí)行流程。

三.預(yù)習(xí)要求:1、學(xué)習(xí)簡單指令集。2、學(xué)習(xí)各指令的操作流程。

四.實(shí)驗(yàn)報(bào)告

1.BLOCK圖

圖1原理圖

內(nèi)存文件:

Addr?0+1?2+3X+5+6?7

000000015002400D0001F0094003100E0

8001E004100A10061008400510028002D

16007B00D0001Eooco001900D0001D00B0

24001300F0000000000000000000000000

3200000000000000000000000000000000

4000000000000000000000000000000000

4800000000000000000000000000000000

5600000000000000000000000000000000

6400000000000000000000000000000000

7200000000000000000000000000000000

80____00000000000000000000000000000000

圖2內(nèi)存文件.Mif

2.程序設(shè)計(jì)

LIBRARYieee;

USEieee.std_logic_1164.ALL;

PACKAGEmypackIS

CONSTANTidle:stdjogic_vector(3DOWNTO0):="0000";

CONSTANTload:stdlogicvector(3DOWNTO0):="0001H;

CONSTANTmove:std_logic_vector(3DOWNTO0):="00l0";

CONSTANTaddx:std_logic_vector(3DOWNTO0):="00ir';

CONSTANTsubp:std_logic_vector(3DOWNTO0):="0100";

CONSTANTandp:std_logic_vector(3DOWNTO0):="0101";

CONSTANTorp:std_logic_vector(3DOWNTO0)

CONSTANTxorp:std_logic_vector(3DOWNTO0):="0111";

CONSTANTshrp:std_logic_vector(3DOWNTO0):="1000";

CONSTANTship:std_logic_vector(3DOWNTO0):="1001";

CONSTANTswap:std_logic_vector(3DOWNTO0):="1010";

CONSTANTjmp:std_logic_vector(3DOWNTO0):="1011";

CONSTANTjz:std_logic_vector(3DOWNTO0):="1100";

CONSTANTread:std_logic_vector(3DOWNTO0)

CONSTANTwrite:std_logic_vector(3DOWNTO0):="1110";

CONSTANTstop:stdjogic_vector(3DOWNTO0):="1111H;

ENDmypack;

LIBRARYieee;

USEieee.std_logic_1164.ALL;

USEieee.std_logic_unsigned.ALL;

USEWORK.mypack.ALL;

-------------------------cpu實(shí)體聲明-----------------------

ENTITYcpu2IS

PORT(

reset:INstdjogc;-清零信號低有效

clock:INstdjogic;一時(shí)鐘信號

Write_Read:OUTstdjogic;一讀寫信號,T為寫

M_address:OUTstd_logic_vector(11DOWNTO0);??地址線

M_data_in:INstd_logic_vector(7DOWNTO0);-數(shù)據(jù)輸入線

Mdata_out:OUTstd_logic_vector(7DOWNTO0);--數(shù)據(jù)輸出線

overflow:OUTstdjogic);一溢出標(biāo)志

ENDcpu2;

..............................cpuRTL級行為描述............

ARCHITECTURERTLofcpu2IS

SIGNALIR:std_logic_vector(15DOWNTO0);-指令寄存器

SIGNALMDR:std_logic_vector(7DOWNTO0);--數(shù)據(jù)寄存器

SIGNALMAR:std_logic_vector(11DOWNTO0);一地址寄存器

SIGNALstatus:intftgftrRANGE0TO6;--狀態(tài)寄存器

BEGIN

status_change:PROCESS(reset,clock,status)

BEGIN

IFreset='O'THENstatus<=0;

ELSIFclock'EVENTANDclock='O'THEN

CASEstatusIS

WHEN0=>

status<=1:

WHEN1=>

IFIR(15DOWNTO12)=StopTHEN

status<=1;

ELSE

status<=2;

ENDIF;

WHEN2=>

CASEIR(15DOWNTO12)IS

WHENRead|Write|Jmp|Jz|Swap=>

status<=3;

WHENOTHERS=>

status<=0;

ENDCASE;

WHEN3=>

IFIR(15DOWNTO12)=SwapTHEN

status<=0;

ELSE

status<=4;

ENDIF;

WHEN4=>

status<=5;

WHEN5=>

CASEIR(15DOWNTO12)IS

WHENRead|Write=>

status<=6;

WHENOTHERS=>

status<=0;

ENDCASE;

WHENOTHERS=>

status<=0;

ENDCASE;

ELSE

NULL;

ENDIF;

ENDPROCESSstatuschange;

seq:PROCESS(reset,clock)

VARIABLEPC:std_logic_vector(11DOWNTO0);--程序計(jì)數(shù)器

VARIABLER0,R1,R2,R3:std_logic_vector(7DOWNTO0);--通用寄存器

VARIABLEA:std_logic_vector(7DOWNTO0);--臨時(shí)寄存器

VARIABLEtemp:stdlogic_vector(8DOWNTO0);-臨時(shí)變量

BEGIN

IF(reset='O')THEN—清零

IR<=(OTHERS=>'0');

PC:=(OTHERS=。);

RO:=(OTHERS=>'0,);

R1:=(OTHERS=>'0');

R2:=(OTHERS=。);

R3:=(OTHERS=>'0');

A:=(OTHERS='。');

MAR<=(OTHERS=。);

MDR<=.:OTHERS=>'0');

ELSIFfclock'eventANDclock='1')THEN

overflow<='O';

CASEstatusIS

WHEN0=>-狀態(tài)0

IR<=M_data_in&"00000000";--取指令

PC:=PC+1;-程序計(jì)數(shù)器加1

WHEN1=>--狀態(tài)1

IF(IR(15DOWNTO12)/=stop)THEN

MAR<=PC;

ENDIF;

CASEIR(15DOWNTO12)IS

WHENload=>

R0:="0000"&IR(11DOWNTO8;;

WHENshlp|shrp=>

CASEIR(11DOWNTO10)IS-RxtoA

WHEN,,00',=>A:=R0;

WHEN"01"=>A:=R1;

WHEN"10M=>A:=R2;

WHENOTHERS=>A:=R3;

ENDCASE;

WHENMove|addx|subp|andp|orp|xorp|Swap=>

CASEIR(9DOWNTO8)IS-RytoA

WHEN"00"=>A:=R0;

WHEN"01'=>A:=R1;

WHEN"10M=>A:=R2;

WHENOTHERS=>A:=R3;

ENDCASE;

WHENOTHERS=>NULL;

ENDCASE;

WHEN2=>--狀態(tài)2

CASEIR(15DOWNTO12)IS

WHENaddx=>-Rx:=Rx+A;

CASEIR(11DOWNTO10)IS

WHEN"00"=>

temp:=(R0(7)&R0(7DOWNTO0))+(A(7)&A(7DOWNTO

0));

R0:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"01"=>

temp:=(R1(7)&R1(7DOWNTO0))+(A(7)&A(7DOWNTO

0));

R1:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"10"=>

temp:=(R2(7)&R2(7DOWNTO0))+(A(7)&A(7DOWNTO

0));

R2:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHENOTHERS=>

temp:=(R3(7)&R3(7DOWNTO0))+(A(7)&A(7DOWNTO

0));

R3:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

ENDCASE;

WHENsubp=>-Rx:=Rx-A;

CASEIR(11DOWNTO10)IS

WHEN"00"=>

temp:=(R0(7)&R0(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1;

R0:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"01'=>

temp:=(R1(7)&R1(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1;

R1:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"10"=>

temp:=(R2(7)&R2(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1;

R2:=temp(7DOWNTO0);

overflow<=temp(8)xorteTip(7);

WHENOTHERS=>

temp:=(R3(7)&R3(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1;

R3:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

ENDCASE;

WHENmove=>

CASEIR(11DOWNTO10)IS

WHEN"00M=>R0:=A;

WHEN"01"=>R1:=A;

WHEN"10M=>R2:=A;

WHENOTHERS=>R3:=A;

ENDCASE;

WHENshrp=>

CASEIR(11DOWNTO10)IS

WHEN"00M=>R0:='O'&A(7DOWNTO1);

WHEN"01"=>R1:='O'&A(7DOWNTO1);

WHEN"10H=>R2:='O'&A(7DOWNTO1);

WHENOTHERS=>R3:=’0,&A(7DOWNTO1);

ENDCASE;

WHENship=>

CASEIR(11DOWNTO10)IS

WHEN"00M=>R0:=A(6DOWNTO0)&'O';

WHEN"01'=>R1:=A(6DOWNTO0)&'O';

WHEN"10'=>R2:=A(6DOWNTO0)&'O';

WHENOTHERS=>R3:=A(6DOWNTO0)&'O';

ENDCASE;

WHENandp=>-Rx:=RxANDA;

CASEIR(11DOWNTO10)IS

WHEN-00H=>R0:=R0ANDA;

WHEN"01"=>R1:=R1ANDA;

WHEN"10M=>R2:=R2ANDA;

WHENOTHERS=>R3:=R3ANDA;

ENDCASE;

WHENorp=>-Rx:=RxORA;

CASEIR(11DOWNTO10)IS

WHEN"00"=>R0:=R0ORA;

WHEN"01M=>R1:=R1ORA;

WHEN"10M=>R2:=R2ORA;

WHENOTHERS=>R3:=R3ORA;

ENDCASE;

WHENxorp=>-Rx:=RxXORA;

CASEIR(11DOWNTO10)IS

WHEN"00"=>R0:=R0XORA;

WHEN"01M=>R1:=R1XORA;

WHEN"10M=>R2:=R2XORA;

WHENOTHERS=>R3:=R3XORA;

ENDCASE;

WHENSwap=>--Swap:RxtoRy;

CASEIR(11DOWNTO8)IS

WHEN"0100"=>R0:=R1;

WHEN"1000"=>R0:=R2;

WHEN"1100"=>R0:=R3;

WHEN"0001H=>R1:=R0;

WHEN"1001M=>R1:=R2;

WHEN"1101"=>R1:=R3;

WHEN"0010"=>R2:=R0;

WHEN"0110"=>R2:=R1;

WHEN"1110"=>R2:=R3;

WHEN"0111"=>R3:=R1;

WHEN"1011"=>R3:=R2;

WHEN"0011"=>R3:=R0;

WHENOTHERS=>NULL;

ENDCASE;

WHENOTHERS=>NULL;

ENDCASE;

WHEN3=>--狀態(tài)3

CASEIR(15DOWNTO12)IS

WHENSwap=>-Swap:AtoRx

CASEIR(11DOWNTO10)IS

WHEN"00"=>R0:=A;

WHEN-01M=>R1:=A;

WHEN"10"=>R2:=A;

WHENOTHERS=>R3:=A;

ENDCASE;

WHENjmp|Jz|Read|Write=>

IR(7DOWNTO0)<=M_data_in;-取雙字節(jié)指令的后半部分

PC:=PC+1;

WHENOTHERS=>NULL;

ENDCASE;

WHEN4=>--狀態(tài)4

CASEIR(15DOWNTO12)IS

WHENjmp=>-無條件轉(zhuǎn)移指令

PC:=IR(11DOWNTO0);

MAR<=IR(11DOWNTO0);

WHENJz=>-條件轉(zhuǎn)移指令

IF(R0="00000000")then

PC:=IR(11DOWNTO0);

MAR<=IR(11DOWNTO0);

else

MAR<=PC;

ENDIF;

WHENRead=>

MAR<=IR(11DOWNTO0);

WHENWrite=>

MARv=IR(11DOWNTO0);

MDR<=RO;

WHENOTHERS=>NULL;

ENDCASE;

WHEN5=>一狀態(tài)5

MAR<=PC;

WHEN6=>--狀態(tài)6

CASEIR(15DOWNTO12)IS

WHENRead=>RO:=M_datajn;

WHENOTHERS=>NULL;

ENDCASE;

ENDCASE;

ENDIF;

ENDprocessseq;

comb:PROCESS(reset,status)

BEGIN

IF(reset='1'ANDstatus=5ANDIR(15DOWNTO12)=Write)THEN

Write_Read<=T;

ELSE

Write_Read<='O';

ENDIF;

ENDPROCESScomb;

Maddress<=MAR;

M_data_out<=MDR;

ENDRTL;

3.仿真波形圖

clock

國A

國ep立?nst|\s?4:?C

囹inst|\s?qB0

囹>nst|\s<aRI

回中〃R2

國R3

回|IB

國cpxC|MAR

囹>nst|?DR

國)nst|st?tus

S

S??q

ovtrQov

¥rxt?_Re4d

圖3波形圖1

clocknjumnRRnnmuuuuuuinnrLnruuuumnRnnnrLnjuumnnnRnjuuuuuu

reset

回0g:IMS\“qA(99X32xgIX20X64Xqq

回c^n2'inttrcIOOXTCOXroo080)KOX⑸/C8OX劃X網(wǎng)X680XEmX】3X劃X580XD80

回cpr£:iRst\"QWwX20X03XWXODXR

回cpxi2.iast\5<-qRI99X32X64

(21“G.IANUQK200X20XuX22

回ep?<2:inti\<MKJ8X次

回eyt^'iikttIK8WOX5100X2800X21doX?KK)XDOCO丫101XX1900XDCCOXwinXCOOJXBOOXFOOO

回CJ^12in?t■ABf,OJDXootX81x010XOUX012x013加*OMXOFX016X017加*018X019KCIA

囹cpu2:iftstWDR99

回cp砂.i皿status

回■_44dr?“(13XHX>x1?X17X18X>9?0X20X2.X笠X23/欲24X”X?

(399

回Lq84X51X28X2DX?BXroXIEXco速X19XWXIDX田弟以13XF。X00

“erfl”

Vialw-R?d

圖4波形圖2

解釋如卜.:

操作碼OP指令指令的助記符操作的內(nèi)容

1R(15..12)格式

00003Idle無操作,PC:=PC+I:(為取下一條指令準(zhǔn)

備地址)

00012LoadDataR0-I;(立即數(shù)I送R0)PC:=PC+1

00101MoveRx.RyRx-(Ry);PCFPC+1

0011

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