LED點(diǎn)陣動(dòng)畫(huà)顯示控制的VHDL程序?qū)崿F(xiàn)

LED點(diǎn)陣動(dòng)畫(huà)顯示控制的VHDL程序?qū)崿F(xiàn)

學(xué)生：胡云龍指導(dǎo)老師：張家波VHDL語(yǔ)言VHDL的英文全稱為very-high-speedintegratedcircuithardwaredescriptionlanguage。1978年底，VHDL被美國(guó)電氣和電子工程師協(xié)會(huì)InstituteofElectricalandElectronicsEngineers(IEEE)和美國(guó)國(guó)防部確認(rèn)為標(biāo)準(zhǔn)硬件描述語(yǔ)言。VHDL特點(diǎn)1.功能強(qiáng)大2.可移植性3.獨(dú)立性4.可操作性5.靈活性設(shè)計(jì)思路1.數(shù)據(jù)文檔讀取2.實(shí)現(xiàn)對(duì)數(shù)據(jù)文檔的讀取控制3.數(shù)據(jù)在LED點(diǎn)陣板顯示LED板送數(shù)LED點(diǎn)陣板電路圖數(shù)字“0”MIF文件格式WIDTH=8;DEPTH=8;ADDRESS_RADIX=BIN;DATA_RADIX=BIN;ADDRESS_RADIX：DATA_RADIXend設(shè)計(jì)模塊流程各種信號(hào)的輸入CLKCLRGO主模塊：接收控制信號(hào)進(jìn)行數(shù)據(jù)處理，并且輸出存儲(chǔ)器輸出數(shù)據(jù)行數(shù)控制以及LED點(diǎn)陣板對(duì)應(yīng)行號(hào)（ROW）數(shù)據(jù)存儲(chǔ)器模塊：根據(jù)主模塊處理結(jié)果進(jìn)行輸出每行所對(duì)應(yīng)的數(shù)據(jù)（COL）每行數(shù)據(jù)（COL）LED點(diǎn)陣板行號(hào)控制（ROW）設(shè)計(jì)程序ENTITYmycnt8_8ISPORT(clk,clr,go:INSTD_LOGIC;----輸入端口clk，clr，gorow:bufferSTD_LOGIC_VECTOR(7DOWNTO0);----行序列輸出端口rowq:bufferSTD_LOGIC_VECTOR(6DOWNTO0));----與存儲(chǔ)器相連接的地址端口qENDmycnt8_8;ARCHITECTURESYNOFmycnt8_8ISsignalcntdata:integerrange0to9;設(shè)計(jì)程序P1:process(go)beginif(go'eventandgo='1')then----高電頻“1”為觸發(fā)態(tài)if(cntdata<9)thencntdata<=cntdata+1;----cntdata參數(shù)小于9，最大值為cntdata+1elsecntdata<=0;----其他情況，輸出顯示“0”的數(shù)據(jù)endif;endif;endprocessP1;設(shè)計(jì)程序when0=>----顯示數(shù)字“0”的時(shí)候if(cnt_addr<7)thencnt_addr:=cnt_addr+1;----cnt_addr加一之后重新賦值于cnt_addr，此段代碼中最大值為7+1fortmpiin7downto1loopp(tmpi)<=p(tmpi-1);endloop;p(0)<='0';q<=q+1;----實(shí)現(xiàn)行數(shù)據(jù)的順序進(jìn)行elsecnt_addr:=0;