后端流程整理

后端流程整理

目錄

1。綜合

2。綜合后仿真

3。布局布線

4。布線后仿真

5o規(guī)則檢查

6oMPW提交數(shù)據(jù)

第一部分綜合［Synthesis］

綜合簡介

綜合按照種類分可以分為邏輯綜合［LogicSynthesis］和物理可知綜合［PhysicalKnowledgeable

Synthesis］?邏輯綜合是指根據(jù)設(shè)計(jì)者的RTLHDL［RegisterTransistorLevelHardware

DescriptionLanguage］原代碼使用綜合工具轉(zhuǎn)換成用目標(biāo)工藝庫表示的門級網(wǎng)表。在特征尺

寸不斷減小的情況下［例如點(diǎn)35工藝及以下］,原來的邏輯綜合變得愈來愈達(dá)不到設(shè)計(jì)者的

要求，因此，新的做法就是把邏輯綜合的結(jié)果先去布局和布線，然后再把其結(jié)果返回給綜合

工具，再一次地進(jìn)行綜合，這時(shí)的綜合已經(jīng)加入了相當(dāng)一部分的物理信息，所以把這步再綜

合的過程稱為物理可知綜合。

綜合按照步驟分可以分成三步：

?Synthesis=translation+optimization+Mapping

residue?1(*hOOOO/

if(highbits??2,bl0>

TargetTechnology

TranslationOptimization+Mapping

alwaysu/iposedgcckK'ki

iRscl_sig)

data_oulllil;

elseif(reseLsig!

data_oulPbO:

elseir(enable)

dala_ouldutajn:

(technulo<{\indepcndenOTargetnetlist

RTLHDL(iHhnohigydependentl

綜合的特點(diǎn)：以時(shí)序路徑為基礎(chǔ)，以約束為準(zhǔn)繩的轉(zhuǎn)換過程。

[Timing-path-BasedandConstraint-Driven]

下面介紹?下綜合部分的工作流程以及工具介紹

ASIC[Application-SpecificIntegratedCircuit]領(lǐng)域里面綜合工具主要有:

Cadence公司的Ambit和新思[Synopsys]公司的DesignCompiler,這里主要介紹后者。

使用DC做證rilog設(shè)計(jì)的綜合工作流程

lo文件和目錄準(zhǔn)備

文件準(zhǔn)備：

RTL設(shè)計(jì)描述文件[VerilogHDL]

CMOS標(biāo)準(zhǔn)單元庫[CSMC06_ver5]

在這里順便介紹一下CMOS標(biāo)準(zhǔn)單元庫：

CSMCCMOS06umStandardCellLibrary

[Version5.0復(fù)旦大學(xué)ASIC國家實(shí)驗(yàn)室開發(fā)，匕海集成電路設(shè)計(jì)與研究中心版權(quán)所有]

構(gòu)成簡介

CTLFCompiledTimingLibrary

containsthetiminglibraryofallthecoreandpadcells

*.tlf-textformatfile

*.ctlf■一binaryformatfile

DEF-DesignExchangeFormat

containsthedefofpowerandgroundnets

*.def???textformat

EXTRACTEDNET

containsSPICE[CDL]netlistofallthecoreandpadcells

GCF-一GeneralConstraintsFormat

containsthelocationofCTLFfiles

LEFLibraryExchangeFormat

containslibraryinformationfbraclassofdesigns.

LIB-StandardcoreandpadcellsdatabaselibraryforDC

containsthefunctionandtiminginformationofcellsanditssymbol.

MAP-Mappingfiles

containstheinformationfbrmatchingoflayoutlayerfromvariesdesignsystems.

SEINI--SiliconEnsembleInitializationfiles

containsthesetupofsomeenvironmentalvariablesinSiliconEnsemble

TECHFILETechnologySpecificInformationfiles

containsthefilesusedtoinitializenewlibraryinICFB.

VERILOGVerilogdescriptionofallthecoreandpadcells

VITALVHDLdescriptionofallthecoreandpadcells

工作目錄準(zhǔn)備

2.啟動(dòng)DC

啟動(dòng)DC一般有三種方式:

圖形界面：

xterm-1□1x|

SunMicrosystemsInc.SunOS5.8GenericPatchOctober2001

server^pwd

/training/tr03

server^Is

CDS?logfilenamesJogpanicjog

DRE工DS.logFind.txtsynopsys.cache.1999.10

_z8051.finaLversionfminitview_command4log

ac_shell4cmd91a8051yaodao

ac.shelljoglibManagerJogzhu51

cdsjibmjg8051

command.lognsmail

server^cd-z8051_fina1_version

server^Is

checkcsmcOGlibmpw_docplace_routertlsynthesis

server^cdsynthesis

server^Id

server^Is

Synthesis.readmereadmesynopsys_dc.l?setup

command?logreportssynopsys_dc_2?setup

dc_setup_filescriptsmandjog

outputsource.codes

server^da&|

按回車鍵,

xterm,|D|x|

server^da&

Cl]16995

server2

DesignAnalyzer<TM>

BehavioralCompiler(TM)

DCProfessional<TM)

DCExpert<TM>

FloorPlanManager(TM)

FPGACompiler(TM)

VHDLCompiler(TM>

HDLCompiler(TM>

LibraryCompiler<TH)

PowerCompiler(TM>

TestCompiler(TM)

TestCompilerPlus(TM)

CTV-Interface

ECOCompiler(TM)

DesignWareDeveloper(TM>

DesignPower<TM>

Version1999.10—Sep02,1999

Copyright<c)1988-1999bySynopsys,Inc.

ALLRIGHTSRESERVED

ThisprogramisproprietaryandconfidentialinformationofSynopsys,Inc.

andmaybeusedanddisclosedonlyasauthorizedinalicenseagreement

controllingsuchuseanddisclosure*

Initializing…

然后跳出主界面:

IHSynopsysDesignAnalyzer

SetupFile瑣”皆知自ttH澈【蝦色聞F"*TwkHelpn

國

OI

1>刃1

囹

圖

Synopsys,Inc.<c>

關(guān)于界面:

AbouttheDesignAnalyzer

Synopsy?DesignAnalyzer

<c)Synopsys1994

WelcometoDesignAnalyzer,thegraphicinterfacetotheSynopsys

familyoflogicsynthesistools?

ThisbriefsummarydescribesDesignAnalyzer,itswindowszandhow

tousevariousfeatures：

-DesignAnalyzerWindow

-UserInterfaceBasics

-SelectingObjects

-DesignAnalyzerCommandWindow

-TypicalSynthesisFlow

SeetheSynopsysdocumentationforacompleteexplanationof

DesignAnalyzerandotherSynopsystools.

ThebasicDesignAnalyzerusermodelis：

1>Youselectadesign,port,cell,net,subdesign,clock>

orotherobject.Validmenusandmenuselectionsare

thenautomaticallyenabled(invalidorinappropriatemenus

andselectionsare"grayedout").

2)Youchooseanappropriateaction,suchassettinga

然后選擇要執(zhí)行的腳本文件:

IHSynopsysDesignAnalyzer-1□1x

泓卬IDie圖力的3儺h3坂*6名碌七m號堂可卜Help

Defaults...

Variables..,

License

“ecuteScript,..

ExecuteFileX

FileName：|runme.scr^

Birectory：r03/_z805Lfina1_version/synthesis/scripts

Cancel|

選擇完成以后，DC就自動(dòng)執(zhí)行所設(shè)定的腳本，完成后顯示如下圖：

回

-回

D,

H

L-

-

r

aHDl

窗

茴

BlDe

0X

茴

2茴

QlDe

0X

茴

m7茴

Q

J

茴

BX茴

.3

D

茴

D茴

dd_16-0

^

^

^

^

1

DesignsView

LeftButton:Select-MiddleButton:Add/ModlfySelect-RightButton:Menu

選擇查看頂層模塊:

ALE

CSB0

CSBL

2JDESTIN__DO(7:0]

T1PORT0IC7：0]NPORT0E

PORT1IC7：0]NPORT1E[7：0]

創(chuàng)

PQRT2IC7：0]NPORT2EC7：0]

PORT3IC7：0]NPORT3EC7：01

z8051uarp

JdRSTNPSEN

SOURCE-DI..0C7：0]PORT0OE7：0]

SOURCE_DI_1[7：0]PORT1OC710]

XTAL1PORT2OC7：0J

PORT3OC7：0J

SOE

SRAN_ADDR【5；0]

SWEB

CurrentDesicm：z8051warpSymbolView

LeftButton：Select-MiddleButton：Add/ModifySelect-RightButton:Menu

查看其下層電路圖:

HHSynopsysDesignAnalyzer,1□1X

空tupFileEditViewAttributesAnalysisToolsHelp

CurrentDesicm：z8051warpSchematicView

LeftButton：Select-MiddleButton：Add/ModifySelect-RightButton:Menu

下圖是完全去除了層次:

回

?

；

一

?

U，?

)

iE

El

“n

。

即可

退出

隨后

xterm，[□]x|

server2

DesignAnalyzer(TM>

BehavioralCompiler<TM)

DCProfessional(TM>

DCExpert(TM)

FloorPlanManager(TM)

FPGACompiler<TM)

VHDLCompiler<TM>

HDLCompiler(TM)

LibraryCompiler<TM>

PowerCompiler(TM>

TestCompiler<TM)

TestCompilerPlus(TM>

CTV-Interface

ECOCompiler<TM)

DesignNareDeveloper<TM)

DesignPower(TH)

Version1999?10—Sep02,1999

Copyright<c)1988-1999bySynopsys,Inc.

ALLRIGHTSRESERVED

ThisprogramisproprietaryandconfidentialinformationofSynopsys,Inc,

andmaybeusedariddisclosedonlyasauthorizedinalicenseagreement

controllingsuchuseanddisclosure.

Initializing.??

Thankyoiu.?

[11Donedesign.analyzer

server%|

另外一種辦法就是使用SETUP/commandwindow,使用include命令導(dǎo)入SCR腳本:

其余的過程和上一面的例子一樣。

使用SCR腳本文件的命令行界面:

-inixi

SunMicrosystemsInc.SunOS5.8GenericPatchOctober2001

server^pud

/training/trOS

server^Is

CDS?logfilenames?logpanic?log

DRE.CDSJogFind.txtsynopsys_cache_1999.10

_z8051_Fina1_uersionfminitmandjog

ac_shell.cmd91Mos1yaodao

ac.shelLloglibManagerJogzhu51

cds.libmjg8051

command?lognsmail

server^cd_z8051-fina1.version

server^Is

checkcsmcOGlibmpw.docplace_routertlsynthesis

server^cdsynthesis

server^Is

Synthesis?readmereadmesynopsys.dc.l?setup

command?logreportssynopsys_dc-2?setup

outputscriptsview_commandjo9

post.syn.simsource_codes

server^dc-shel1-f/scripts/runme?scrIteevieu4log|

進(jìn)入以后，系統(tǒng)提示符變成：dc_shell>,然后退出:

xterm,1□!x|

tobreakatimingloop<0PT-314)

Warning：Disablingtimingarcbetweenpins'CK'andZQZoncellzuPMU/XTAL_CTRL_reg

tobreakatimingloop(OPT-314)

Warning：Disablingtimingarcbetweenpins'CK'and'QN'oncellzuPMU/XTAL.CTRL-re

tobreakatimingloop(OPT-314)

Information：Designzz8051warpzhas3.63432+06paths?(WC-13)

Information：Theconstraintfilehas'1/pathconstraints*(HC-14)

1

write.sdf?/output/sdf/z8051warp_syn_v21?sdf

Information：Annotatedzceirdelaysareassumedtoincludeloaddelay*(UID-282)

Information：Writingtiminginformationtofilez/trainin9/tr03/_z8051.fina1_versio

51warp_syn_v21?sdF'?<WT-3>

1

write_sdf-version1.0?/output/sdf/z8051uiarp_syn_vl0?sdf

Information：Annotated'cell'delaysareassumedtoincludeloaddelay*(UID-282)

Information：Writingtiminginformationtofile/training/tr03/_z8051_fina1_versio

51warp_syn_ul0?sdF'?<WT-3>

1

reportsiming-delaymax>?/reports/zSOSlwarp-s1owest-path2?rpt

1

report_timing-delaymin?4/reports/z8051warp_s1owest_path2?rpt

1

report_ce11>?/reports/z8051warp_ce1l_num_area?rpt

1

report-constraint-all.violators>?/reports/z8051warp_any_timing_violation*rpt

1

dcshell>quit|

使用TCL腳本執(zhí)行的命令行界面:

xterm■x|

server^pwd

/trainin9/tr03/-z8051_fina1_ve「sion/synthesis

serverNIs

Synthesis.readmereadmesynopsys_dc_l?setup

commandJogreportssynopsys_dc_2?setup

outputscriptsviewjog

post-syn.slmsource-codesmand?log

server^dc_shell-t|

使用source命令導(dǎo)入TCL腳本語言:

xterm,1□!x|

BehavioralCompiler(TM)

DCProfessional<TH>

DCExpert<TM>

FloorPlanManager(TM)

FPGACompiler(TM)

VHDLCompiler(TM>

HDLCompiler(TM)

LibraryCompiler<TM)

PowerCompiler<TM)

TestCompiler(TM)

TestCompilerPlus<TM>

CTV-Interface

ECOCompiler(TM)

DesignUareDeveloper<TM>

DesignPower(TM)

Version1999?10—Sep02z1999

Copyright(c)1988-1999bySynopsys,Inc.

ALLRIGHTSRESERVED

ThisprogramisproprietaryandconfidentialinformationofSynopsys,Inc.

andmaybeusedanddisclosedonlyasauthorizedinalicenseagreement

controllingsuchuseanddisclosure*

Initializing..?

dcshell-t>source?/scripts/runme?tc11

進(jìn)入以后，系統(tǒng)提示符變成：deshell-t>,然后退出:

xterm

dc-shell-t>quit

Thankyou…

server^|

DC啟動(dòng)配置文件：

.sysnopsysdc.setup

這個(gè)文件的功能是對DC運(yùn)行的所有環(huán)境變量進(jìn)行設(shè)置，主要包括以下幾個(gè)方面:

Site-SpecificVariables

SystemVariableGroup

CompileVariableGroup

MultibitVariableGroup

EstimatorVariableGroup

SyntheticLibraryGroup

InsertTestVariableGroup

AnalyzeScanWriableGroup

BSDVariableGroup

TestManagerVariableGroup

TestSimVariableGroup

TestDRCVariableGroup

TestVariableGroup

JTAGVariableGroup(associatedwiththeinsertjtagcommand)

CreateTestPattemsVariableGroup

WriteTestVariableGroup

SchematicandEDIFandHDLVariableGroup

EDIFandIOVariableGroup

PlotVariableGroup

IOVariableGroup

HdlandVhdlioVariableGroup

ViewVariableGroup

LinkstolayoutVariableGroup

PowerVariableGroup

BCVariableGroup

Aliasesforbackwardscompatibilityorconvenience

下面這個(gè)是簡化的一個(gè)版本：

###############################################################################

#ThisisaTcl-sscriptworksforDC-SHaswellasforDC-Tcl

#Setthetechnologyandlinklibrarieshere:

settargetlibraryHcsmc06core.db"

setlink_library”*csmc06core.db"

setsymbol_library"csmc06core.sdbn

#SettingupDesignWarecachereadandwrite

#directoriestospeedupcompile.

setcache_write~

setcacheread$cache_write

#TellDCwheretolookforfiles

#Use"set"command(insteadoflappend)tokeepcompatibilitywithDesignAnalyzer

setsearch_path"Ssearchpath../csmc061ib/ver5/lib./scripts./source_codesn

#Alias

aliasrc"reportconstraint-all_violatorsn

aliasrt"report_timingn

aliash"history"

setview_script_submenu_items\

{"RemoveAllDesign""removedesign-designs**}

historykeep100

#specifydirectoryforintermediatefilesfromanalyze

define_design_libDEFAULT-path./analyzed

#suppressDrivingcellwarning

suppress_message{UID-401}

DC運(yùn)行腳本：

read-formatverilog./source_codes/z8051warp,v

read-formatverilog./sourcecodes/zcOO1ex.v

read-formatverilog./source_codes/zc002ex.v

read-formatverilog7source_codes/zc003ex.v

read-formatverilog7source_codes/zc004ex.v

read-formatverilog./source_codes/zc005ex.v

read-formatverilog./source_codes/zc006ex.v

read-formatverilog./source_codes/zc007ex.v

read-formatverilog./source_codes/zc008ex.v

read-formatverilog7source_codes/zc009ex.v

read-formatverilog7source_codes/zcO1Oex.v

read-formatverilog./sourcecodes/zcOllex.v

read-formatverilog./source_codes/zcO12ex.v

read-formatverilog./source_codes/zcO13ex.v

read-formatverilog./source_codes/zcO14ex.v

read-formatverilog./sourcecodes/zcO15ex.v

read-formatverilog./sourcecodes/zcO16ex.v

read-formatverilog./sourcecodes/zcO17ex.v

read-formatverilog./sourcecodes/zcO18ex.v

read-formatverilog./sourcecodes/zcO19ex.v

read-formatverilog./source_codes/zc020ex.v

read-formatverilog./source_codes/zc021ex.v

read-formatverilog./source_codes/sraml28.v

read-formatverilog./source_codes/z8051warpdefs.v

currentdesignz8051warp

setwireloadmodetop

setwireloadmodel-namen0xl50k"-librarycsmc06core

link

uniquify

currentdesignz8051warp

createclock-period40-namextall-waveform{0,20}find(port,XTAL1)

setinputdelay1-max-clockxtallall_inputs()-find(port,XTAL1)

set_output_delay1-max-clockxtallall_outputs()

set_clock_uncertainty0.3find(port,XTAL1)

set_clock_latency1find(port,XTAL1)

setdonttouchnetworkXTAL1

set_driving_cell-libcsmc06core.db:csmc06core-lib_cellAN02D1-pinAall_inputs()-find(port,

XTAL1)

setload10.0*load_of(csmc06core.db:csmc06core/ND02DlArN)all_outputs()

setfixmultipleportnets-all-bufier_constants

currentdesignzc004ex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

setc1ockuncertainty0.3find(port,CCLK)

setdonttouchnetworkCCLK

current_designzc005ex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

set_clock_uncertainty0.3find(port,CCLK)

set_dont_touch_networkCCLK

cuiTentdesignzc006ex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

setc1ock_uncertainty0.3find(port,CCLK)

setdonttouchnetworkCCLK

currentdesignzc008ex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

set_clock_uncertainty0.3find(port,CCLK)

setdonttouchnetworkCCLK

currentdesignzc009ex

createclock-period40-namecclk-waveform{0,20}find(port,CCLK)

set_clock_uncertainty0.3find(port,CCLK)

set_dont_touch_networkCCLK

current_designzcOlOex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

createclock-period40-namesclk-waveform{0,20}find(port,SCLK)

create_clock-period40-namensclk-waveform{0,20}find(port,NSCLK)

set_clock_uncertainty0.3find(port,{CCLKSCLKNSCLK})

setdonttouchnetwork{CCLKSCLKNSCLK)

currentdesignzcO12ex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

create_clock-period80-namepclk-waveform{0,60}find(port,PCLK)

set_clock_uncertainty0.3find(port,{CCLKPCLK})

setdonttouchnetwork{CCLKPCLK}

current_designzc014ex

create_clock-period40-namedeIk-waveform{0,20}find(port,DCLK)

setclockuncertainty0.3find(port,DCLK)

set_dont_touch_networkDCLK

current_designzcO15ex

createclock-period40-namextall-waveform{0,20}find(port,XTAL1)

setclockuncertainty0.3find(port,XTAL1)

set_dont_touch_networkXTAL1

currentdesignzcO16ex

createclock-period40-namecclk-waveform{0,20}find(port,CCLK)

setclockuncertainty0.3find(port,CCLK)

setdonttouchnetworkCCLK

currentdesignzcO17ex

createclock-period40-namecclk-waveform{0,20}find(port,CCLK)

createclock-period40-namesclk-waveform{0,20)find(port,SCLK)

setc1ock_uncertainty0.3find(port,{CCLKSCLK})

setdonttouchnetwork{CCLKSCLK}

currentdesignzc019ex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

create_clock-period80-namepclk-waveform{0,60}find(port,PCLK)

set_clock_uncertainty0.3find(port,{CCLKPCLK})

set_dont_touch_network{CCLKPCLK}

currentdesignzc020ex

create_clock-period40-namecclk-waveform{0,20}find(port,CCLK)

createclock-period40-namesclk-waveform{0,20}find(port,SCLK)

create_clock-period80-namepclk-waveform{0,60}find(port,PCLK)

set_clock_uncertainty0.3fin(l(port,{CCLKSCLKPCLK})

set_dont_touch_network{CCLKSCLKPCLK}

currentdesignzc021ex

createclock-period40-namecclk-waveform{0,20}find(port,CCLK)

set_clock_uncertainty0.3find(port,CCLK)

set_dont_touch_networkCCLK

currentdesignsraml28

create_clock-period40-namensclk-waveform{0,20}find(port,NSCLK)

set_clock_uncertainty0.3find(port,NSCLK)

set_dont_touch_networkNSCLK

currentdesignz8051warp

/**/

setmulticyclepath4-setup-fromnuPDR/OPCODE_reg*n-tonuCSFR/B_reg*H

set_multicycle_path4-setup-fromnuPDR/OPCODE_reg*n-toHuCSFR/PSW_reg*n

set_multicycle_path4-setup-fromnuPDR/OPCODE_reg*n-tonuDMI/I_SPTCON_reg*H

setmulticyclepath4-setup-fromnuPDR/OPCODE_reg*n-to

“uPMI/DATA_POINTER_0_reg*”

setmulticycle_path4-setup-fromHuPDR/OPCODE_reg*n-to

“uPMI/DATA_POINTER_l_reg*”

set_multicycle_path4-setup-fromnuPDR/OPCODE_reg*n-to”uPMI/I_DPS_reg*”

set_multicycle_path4-setup-fromnuPDR/OPCODE_reg*n-tonuPMI/I_DPGS_reg*H

setmulticyclepath4-setup-fromnuPDR/OPCODE_reg*n-tonuPMI/DPTR_PAGER_O_reg*n

set_multicycle_path4-setup-fromnuPDR/OPCODE_reg*H-toHuPMI/DPTR_PAGER_l_reg*M

setmulticycle_path4-setup-fromMuPDR/OPCODE_reg*n-tonuSTM/I_CKCON_reg*M

set_multicycle_path4-setup-fromnuPDR/OPCODE_reg*n-tonuSTM/I_SWRST_reg*n

set_multicycle_path4-setup-f