超大規(guī)模集成電路第六次作業(yè)2016秋-段成華

ThefollowingfigureshowsaC2MOSbaseddual-edgetriggeredregister.Itsadvantageisthatalowerfrequencyclock(halfoftheoriginalrate)isdistributedforthesamefunctionalthroughput,resultinginpowersavingsintheclockdistributionnetwork.CalculatethetimingparametersofsetuptimetSU,holdtimetHandpropagationdelaytCOoftheregisterwithrespecttotherisingedgeoftheclockCLK,giventhattheinverterdelayistINV.AssumethatthetransistorsarewiththeminimumsizeandC=20fF.Verifythefunctionofthedual-edgetriggeredregisteranditstimingparametersin(1)byusingHSPICEandTSMC0.18umCMOStechnologymodelwith1.8Vpowersupply.DeterminerespectivelythemaximumworkfrequencyfmaxoftheregisterbyHSPICEsimulation.Determinethemaximumfreshcycleoftheregister.Solution:、C2MOS電路對(duì)時(shí)鐘重疊不敏感所以CLK和CLK’因反相器導(dǎo)致的延時(shí)問題不予考慮。CLK在上升沿之前為低電平，假設(shè)輸入D為1，M9，M10和M1導(dǎo)通，則Y為0，所以tSU=tINV（類似反相器的傳播延時(shí)）+tINV（CLK到CLK’反相器導(dǎo)致的延時(shí)）=2tINV；由于上升沿到來后CLK為高電平，M9和M10關(guān)斷，所以在時(shí)鐘變?yōu)楦唠娖胶筝斎氲娜魏巫兓疾粫?huì)影響輸出，所以tH=0；當(dāng)CLK上升沿到來，則M14，M13和M12導(dǎo)通Y=0反向輸出到Q（為1），所以tCO=tINV（類似反相器的傳播延時(shí)）+tINV（CLK到CLK’反相器導(dǎo)致的延時(shí)）=2tINV?？梢钥闯鯟2MOS電路相比于靜態(tài)電路延時(shí)很小。、代碼如下：.titleC2MOSLOGICOFINVERTERS.lib'C:\synopsys\Hspice_D-2010.03-SP1\tsmc018\mm018.l'TT*set0.18umlibrary.optionspost=2list.temp27.globalvddVddvddgnd1.8vclknvclkn00.9pulse0.01.81500p5p5p2990p6000pvinvin00.9PWL0p0,1280p0,1285p1.8C1voutxgnd20fC2voutygnd20fC3vqgnd20f.subcktPN-TYPE-INV1clknclkpDoutn2n1wn=0.35uwp=1.0ut=0.5um1n2DgndgndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outclknn2gndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm3outclkpn1vddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'm4n1DvddvddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.ends.subcktPN-TYPE-INV2clknclkpDoutwn=0.35uwp=1.0ut=0.5um1n2DgndgndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outclknn2gndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm3outclkpn1vddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'm4n1DvddvddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.ends.subcktPN-TYPE-tINVclkpclknoutn2n1wn=0.35uwp=1.0ut=0.5um1outclkpn2gndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outclknn1vddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.ends.subcktinvinoutwn=0.35uwp=1.0ut=0.5um1outingndgndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outinvddvddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.endsX1vclknvclkpinvX2vclknvclkpvinvoutxn2n1PN-TYPE-INV1X3vclkpvclknvoutxvqPN-TYPE-INV2X4vclkpvclknvoutyn2n1PN-TYPE-tINVX5vclknvclkpvoutyvqPN-TYPE-INV2.op.tran5p18000p.meastranvqmaxmaxv(vq)from=50pto=18000p.meastranvqminminv(vq)from=50pto=18000p.meastrantplh_Tco+trigv(vclkn)+val=0.9+rise=1+targv(vq)+val='0.5*(vqmax-vqmin)+vqmin'+rise=1.printdcv(vclkn)v(vin)v(voutx)v(vouty)v(vq).end周期為6000ps，設(shè)置建立時(shí)間為220ps則得到如下測(cè)量數(shù)據(jù)和圖形：周期為6000ps，設(shè)置建立時(shí)間為215ps則得到如下測(cè)量數(shù)據(jù)和圖形：對(duì)比以上兩圖當(dāng)tSU兩=215ps時(shí)候電壓只達(dá)到了0.84V，而220ps時(shí)候達(dá)到了1.2364V，所以建立時(shí)間近似為220ps。而對(duì)比于一個(gè)反相器帶載為20fF的延時(shí)約為110ps，所以預(yù)測(cè)的建立時(shí)間近似正確。為了為了使得測(cè)量的tCO更準(zhǔn)確，將建立時(shí)間給的足夠設(shè)為500ps，得到測(cè)量數(shù)據(jù)和圖形如下：分析如下：得到的延時(shí)時(shí)間為284ps，也約為一個(gè)反相器延時(shí)的二倍，延時(shí)偏大的原因可能和中間一級(jí)的負(fù)載電容有關(guān)。根據(jù)上圖可以知道當(dāng)上升沿到來則直接將輸入信號(hào)變?yōu)?，發(fā)現(xiàn)輸出vp正常，所以不需要保持時(shí)間即tH=0.、周期為500ps，CLK高電平期間作為輸入vin的建立時(shí)間，切出入vin恰好為上升沿開始位置，這樣可以使整個(gè)高電平作為建立時(shí)間tSU，正常來說周期為440ps是可以的，實(shí)測(cè)到周期為500ps時(shí)候，下降沿觸發(fā)傳遞到vq，到低電平結(jié)束vq最大為1V，所以周期不可能再小了，再小整個(gè)建立時(shí)間不夠，D是無(wú)法傳輸?shù)絏處的，同時(shí)傳遞時(shí)間也不夠，整個(gè)觸發(fā)器處于無(wú)法正常工作的狀態(tài)