VHDL和數(shù)字集成電路設(shè)計第四章算數(shù)邏輯單元-加法器和乘法器課件

第四章算數(shù)邏輯單元4.1加法器4.2乘法器VHDL與數(shù)字集成電路設(shè)計加法器設(shè)計加法運算從最低位開始，逐步向高位進(jìn)行；每一位相加時，產(chǎn)生1位結(jié)果（s），同時產(chǎn)生1位進(jìn)位（c）；最低位相加時，只需要考慮2個數(shù)據(jù)的相加：半加；其余位相加時，需要考慮3個數(shù)據(jù)的相加：全加。4.1加法器、算數(shù)邏輯單元加法器設(shè)計半加器4.1加法器、算數(shù)邏輯單元加法器設(shè)計全加器4.2加法器、算數(shù)邏輯單元利用半加單元設(shè)計全加器4.2加法器、算數(shù)邏輯單元可擴(kuò)展的串行加法器：采用全加器級聯(lián)構(gòu)成4.2加法器、算數(shù)邏輯單元4位串行加法器：ASIC設(shè)計第1級采用半加；最高級取消進(jìn)位。4.2加法器、算數(shù)邏輯單元8Full-Adder9TheBinaryAdder10ExpressSumandCarryasafunctionofP,G,DDefine3newvariablewhichONLYdependonA,BGenerate(G)=ABPropagate(P)=A?BDelete=A

BCanalsoderiveexpressionsforSandCobasedonDandP

Propagate(P)=A+BNotethatwewillbesometimesusinganalternatedefinitionfor11TheRipple-CarryAdderWorstcasedelaylinearwiththenumberofbitsGoal:Makethefastestpossiblecarrypathcircuittd=O(N)tadder=(N-1)tcarry+tsum12ComplimentaryStaticCMOSFullAdder28Transistors13InversionProperty14MinimizeCriticalPathbyReducingInvertingStagesExploitInversionProperty15ABetterStructure:TheMirrorAdder16TransmissionGateFullAdder17ManchesterCarryChain18ManchesterCarryChain19Carry-BypassAdderAlsocalled

Carry-Skip20Carry-BypassAdder(cont.)tadder=tsetup+Mtcarry+(N/M-1)tbypass+(M-1)tcarry+tsum21CarryRippleversusCarryBypass22Carry-SelectAdder23CarrySelectAdder:CriticalPath24LinearCarrySelect25SquareRootCarrySelect26LookAhead-BasicIdea

27Look-Ahead:TopologyExpandingLookaheadequations:Alltheway:28LogarithmicLook-AheadAdder29CarryLookaheadTreesCancontinuebuildingthetreehierarchically.30TreeAdders16-bitradix-2Kogge-Stonetre