太原理工大學(xué)eda課程設(shè)計(jì)交通燈控制器

/本科實(shí)驗(yàn)報(bào)告課程名稱(chēng)：CPLD/FPGA應(yīng)用設(shè)計(jì)課設(shè)題目：交通燈控制器交通燈控制器一、設(shè)計(jì)要求設(shè)計(jì)一個(gè)由一條主干道和一條支干道的十字路口的交通燈控制器,具體要求如下：<1>主、支干道各設(shè)有一個(gè)綠、黃、紅指示燈,兩個(gè)顯示數(shù)碼管。<2>主干道處于常允許通行狀態(tài),而支干道有車(chē)來(lái)才允許通行。當(dāng)主干道允許通行亮綠燈時(shí),支干道亮紅燈。而支干道允許通行亮綠燈時(shí),主干道亮紅燈。<3>當(dāng)主、支道均有車(chē)時(shí),兩者交替允許通行,主干道每次放行45s,支干道每次放行25s,由亮綠燈變成亮紅燈轉(zhuǎn)換時(shí),先亮5s的黃燈作為過(guò)渡,并進(jìn)行減計(jì)時(shí)顯示。二、設(shè)計(jì)方案1基本原理<1>設(shè)置支干道有車(chē)開(kāi)關(guān)SB。<2>系統(tǒng)中要求有45秒、25秒和5秒三種定時(shí)信號(hào),需要設(shè)計(jì)三種相應(yīng)的計(jì)時(shí)顯示電路。計(jì)時(shí)方法為倒計(jì)時(shí)。定時(shí)的起始信號(hào)由主控電路給出,定時(shí)時(shí)間結(jié)束的信號(hào)輸入到主控電路。<3>主控制電路的輸入信號(hào)一方面來(lái)自車(chē)輛檢測(cè),另一方面來(lái)自45秒、25秒、5秒的定時(shí)到信號(hào)；輸出有計(jì)時(shí)啟動(dòng)信號(hào)〔置計(jì)數(shù)起始值和紅綠燈驅(qū)動(dòng)信號(hào)。<4>狀態(tài)轉(zhuǎn)移如圖所示,用狀態(tài)機(jī)描述。狀態(tài)轉(zhuǎn)移圖<5>模塊結(jié)構(gòu)模塊結(jié)構(gòu)圖2設(shè)計(jì)框圖交通燈控制器原理框圖如下圖所示,包括置數(shù)模塊、計(jì)數(shù)模塊、主控制器模塊和譯碼器模塊。置數(shù)模塊將交通燈的點(diǎn)亮?xí)r間預(yù)置到置數(shù)電路中,計(jì)數(shù)模塊以秒為單位倒計(jì)時(shí),當(dāng)計(jì)數(shù)值減為零時(shí),主控電路改變輸出狀態(tài),電路進(jìn)入下一個(gè)狀態(tài)的倒計(jì)時(shí)。其中,核心部分是主控制模塊。主控制器主控制器清零紅綠黃特殊狀態(tài)紅綠黃定時(shí)計(jì)數(shù)器置數(shù)器譯碼器顯示器三、實(shí)驗(yàn)設(shè)備計(jì)算機(jī)一臺(tái)操作系統(tǒng)：WINDOWSXP軟件：ispDesignEXPERTSystem硬件：1016E開(kāi)發(fā)板四、設(shè)計(jì)步驟1打開(kāi)ispEXPERT軟件,建立一個(gè)新的工程JTD單擊菜單File→NewProject,輸入工程路徑,工程名2建立VHDL文件單擊File→New菜單項(xiàng),選擇VHDLFile選項(xiàng),單擊OK按鈕以建立VHDL文件,分別建立主控制器模塊程序的vhd文件JTDKZ.vhd、計(jì)數(shù)器模塊程序的vhd文件jsq.vhd、七段譯碼器程序的vhd文件yima7.vhd和主程序的vhd文件zhu.vhd。a主控制器模塊LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYJTDKZISPORT<CLK,SB,cnt,RST:INSTD_LOGIC;en,MR,MY,MG,BR,BY,BG:OUTSTD_LOGIC;din:outSTD_LOGIC_vector<7downto0>>;ENDENTITYJTDKZ;ARCHITECTUREARTOFJTDKZISTYPESTATE_TYPEIS<A,B,C,D>;SIGNALp_STATE,n_state:STATE_TYPE;BEGINreg:PROCESS<CLK,rst>ISBEGINifrst='1'thenp_STATE<=A;ELSIF<CLK'EVENTANDCLK='1'>THENp_STATE<=n_state;ENDIF;endprocessreg;com:PROCESS<sb,cnt,p_state>beginCASEp_STATEISWHENA=>MR<='1';MY<='1';MG<='0';BR<='0';BY<='1';BG<='1';IF<SBANDcnt>='1'THENn_STATE<=B;din<="00000101";EN<='0';ELSEn_STATE<=A;din<="01000101";EN<='1';ENDIF;WHENB=>MR<='1';MY<='0';MG<='1';BR<='0';BY<='1';BG<='1';IFcnt='1'THENn_STATE<=C;din<="00100101";EN<='0';ELSEn_STATE<=B;din<="01000101";EN<='1';ENDIF;WHENC=>MR<='0';MY<='1';MG<='1';BR<='1';BY<='1';BG<='0';IFcnt='1'THENn_STATE<=D;din<="00000101";EN<='0';ELSEn_STATE<=C;din<="01000101";EN<='1';ENDIF;WHEND=>MR<='0';MY<='1';MG<='1';BR<='1';BY<='0';BG<='1';IFcnt='1'THENn_STATE<=A;din<="01000101";EN<='0';ELSEn_STATE<=D;din<="01000101";EN<='1';ENDIF;ENDCASE;ENDPROCESScom;ENDARCHITECTUREART;b計(jì)數(shù)器模塊LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYjsqISPORT<en,RST:INSTD_LOGIC;Din:INSTD_LOGIC_VECTOR<7DOWNTO0>;CLK:INSTD_LOGIC;Cnt:OUTSTD_LOGIC; QH,QL:BUFFERSTD_LOGIC_VECTOR<3DOWNTO0>>;ENDENTITYjsq;ARCHITECTUREARTOFjsqISBEGINcnt<='1'WHEN<QH="0000"ANDQL="0000">ELSE'0';PROCESS<CLK,en,RST>BEGINIFRST='1'THENQH<="0100";QL<="0101";ELSIFCLK'EVENTANDCLK='1'THENIFen='0'THENQH<=Din<7DOWNTO4>;QL<=Din<3DOWNTO0>;elsIFQL=0THENQL<="1001";IFQH=0THENQH<="1001";ELSE QH<=QH-1;ENDIF;ELSEQL<=QL-1;ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTUREART;c7段譯碼器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYyima7ISPORT<A:INSTD_LOGIC_VECTOR<3DOWNTO0>;LED7S:OUTSTD_LOGIC_VECTOR<6DOWNTO0>>;END;ARCHITECTUREartOFyima7ISBEGINPROCESS<A>BEGINCASEAISWHEN"0000"=>LED7S<="1000000";WHEN"0001"=>LED7S<="1111001";WHEN"0010"=>LED7S<="0100100";WHEN"0011"=>LED7S<="0110000";WHEN"0100"=>LED7S<="0011001";WHEN"0101"=>LED7S<="0010010";WHEN"0110"=>LED7S<="0000010";WHEN"0111"=>LED7S<="1111000";WHEN"1000"=>LED7S<="0000000";WHEN"1001"=>LED7S<="0010000";WHENOTHERS=>LED7S<="1111111";ENDCASE;ENDPROCESS;END;d頂層鏈接文件LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYJTDISPORT<CLK,SB,RST:INSTD_LOGIC;LED1,LED2,LED3,LED4,LED5,LED6:OUTSTD_LOGIC;SEG1:OUTSTD_LOGIC_VECTOR<6DOWNTO0>;SEG2:OUTSTD_LOGIC_VECTOR<6DOWNTO0>>;ENDJTD;ARCHITECTUREBEHAVIORALOFJTDISSIGNALE:STD_LOGIC;SIGNALCN:STD_LOGIC;SIGNALDI:STD_LOGIC_VECTOR<7DOWNTO0>;SIGNALYIMA1,YIMA2:STD_LOGIC_VECTOR<3DOWNTO0>;COMPONENTJTDKZISPORT<CLK,SB,cnt,RST:INSTD_LOGIC;en,MR,MY,MG,BR,BY,BG:OUTSTD_LOGIC;din:outSTD_LOGIC_vector<7downto0>>;ENDCOMPONENT;COMPONENTJSQISPORT<en,RST:INSTD_LOGIC;Din:INSTD_LOGIC_VECTOR<7DOWNTO0>;CLK:INSTD_LOGIC;Cnt:OUTSTD_LOGIC; QH,QL:BUFFERSTD_LOGIC_VECTOR<3DOWNTO0>>;ENDCOMPONENT;COMPONENTYIMA7ISPORT<A:INSTD_LOGIC_VECTOR<3DOWNTO0>;LED7S:OUTSTD_LOGIC_VECTOR<6DOWNTO0>>;ENDCOMPONENT;BEGINU0:JTDKZPORTMAP<CLK,SB,CN,RST,E,LED1,LED2,LED3,LED4,LED5,LED6,DI>;U1:JSQPORTMAP<E,RST,DI,CLK,CN,YIMA1,YIMA2>;U2:YIMA7PORTMAP<YIMA1,SE