DRAM內(nèi)存顆粒測(cè)試簡(jiǎn)介課件

IntroductiontoDRAMTesting---DRAMinsideteam---2015.MayAgendaBasisofTestingTypicalDRAMTestingFlowBurn-inDCTest(Open/Short,Leakage,IDD)FunctionalTest&TestPatternSpeedTestDRAMManufactureWaferAssemblyFinalTestingFinalProductWhyTesting?ToscreenoutdefectWaferdefectAssemblydefectMakesureproductmeetspecofcustomerVoltageguardbandTemperatureguardbandTimingguardbandComplextestpatternCollectdatafordesign&processimprovementQualityReliabilityCostEfficiencyICTestMethodologyICTesterPPSDriverComparatorDUT**DUT=DeviceUnderTestPowerSupplyOutputInputTestingofaDUT:1.ToconnectPPS,Driver,Comparator&GND.2.ToapplypowertoDUT.3.ToinputdatatoDUT(Address,ControlCommand,Data)4.Tocompareoutputwith“expectvalue”andjudgePASS/FAILBasicTestSignalDigitalWaveformElementsLogicVoltageTimingTypicalDRAMFinalTestFlowBurn-inMBT(MonitorBurninTest):StresstoscreenoutEarlyFailuresTBT(TestBurninTest):LongtimepatterntestVeryLowSpeed(5-20MHz),HighParallelTest(10-20Kpcs/oven),LowCostCoreTestDCTestFunctionalTestLowSpeed(DDR3@667MHz),TypicaltesterAdvantestT5588+512DUTHiFixSpeedTestSpeed&ACTimingTestFullSpeed(DDR3@1600MHzandabove),AdvantestT5503+256DUTHiFixBackendMarkingBallScanVisualInspectionBakingVacuumPackDRAMBurn-in(MBT) MBTistostressICandscreenoutearlyfailuresHighTemperatureStress(125degC)HighVoltageStressStressfulPatternBIOperationTimeFailureRateInfantMortalityNormalLifeWornoutNewproductMatureproductBathCurveDRAMBurn-in(TBT)TBTisforlongtimetestpatternsMultipletemperaturetested(e.g.88’C,25’C,-10’C)LongtesttimeatlowspeedPatternscoverallcellarraysNoStressfulconditionHighparalleltestcount,lowcostBothMBTandTBTdoesNOTtestDC(AndoOven)DRAMAdvantestTestDCTestOpen/ShorttestLeakagetestIDDtestFunctionalTest(CoreTest)Differentparameter&PatternforeachfunctionTocheckDRAMcanoperatefunctionallySpeedTestTimingtest@differentspeedgradeDCTestDCTestMethod:ISVM:

ISource

VMeasureVSIM

VSource

IMeasureVCCVCCDCTest–OpenShortPurpose:

CheckconnectionbetweenpinsandtestfixtureCheckifpintopinisshortinICpackageCheckifpintowaferpadhasopeninICpackageCheckifprotectiondiodes

workondie

ItisaquickelectricalchecktodetermineifitissafetoapplypowerAlsocalledContinuityTestDCTest–OpenShortFailureMode:a)Wafer

Problem

Defectofdiodeb)AssemblyProblem

WirebondingSolderballc)ContactProblemSocket

issueCoreCircuitDefectivediodeSocketPogoPindefectWiretouchedDCTest–OpenShortO/STestCondition:ProcedureGroundallpins(includingVDD)UsingPMUforce100uA,onepinatatimeMeasurevoltageFailopentestifthevoltageisgreaterthan1.5VFailshorttestifthevoltageislessthan0.2V100uA0.65VPMUforcesenseforceMeasureVss=0Vdd=0100uAFailOpenPassFailShort>1.5V<0.2VISVMOther=0Typical0.65VDCTest–OpenShortO/STestCondition:ProcedureGroundallpins(includingVDD)UsingPMUforce–100uA,onepinatatimeMeasurevoltageFailopentestifthevoltageislessthan–1.5VFailshorttestifthevoltageisgreaterthan–0.2VFailShortPassFailOpen>–0.2V<–1.5V-100uA-0.65VPMUforcesenseforceMeasureVss=0Vdd=0-100uAISVMOther=0Typical-0.65VDCTest–LeakagePurpose:

VerifyresistanceofpintoVDD/VSSishighenoughVerifyresistanceofpintopinsishighenoughIdentifyprocessprobleminCMOSdeviceDCTest–LeakageILIH/ILIL:InputLeakageHigh/LowToverifyinputbuffersofferahighresistanceNopreconditioningpatternappliedILOH/ILOL:OutputLeakageHigh/LowToverifytri-stateoutputbuffersofferahighresistanceinoffstateTestrequirespreconditioningpatternPerformedonlyonthree-stateoutputsandbi-directionalpinsDCTest–LeakageFailureMode:a)Wafer

problemb)Assemblyproblemc)SocketContactproblem(short)DiecrackBalltouch(Short)DCTest–InputLeakageLowTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditionallinputpinstologic‘1’(highvoltage)UsingPMU(ParametricMeasureUnit)forceGroundtotestedpinWaitfor1to5msecMeasurecurrentoftestedpinFailIILtestifthecurrentislessthan–1.5uAPassFail<–1.5uA0V-10nAPMUforceMeasureVss=0VDDmaxILILVLSICore“0”“1”allinputpins=2.3VOFFONDCTest–InputLeakageHighTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditionallinputpinstologic‘0’(Lowvoltage)UsingPMUforceVDDMAXtotestedpinWaitfor1to5msecMeasurecurrentoftestedpinFailIIHtestifthecurrentisgreaterthan+1.5uAPassFail>

1.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILIHVLSICore“1”“0”allinputpins=0VONOFFDCTest–OutputLeakageLowTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditiontheDUTtotristatewithspecificpatternWaitaspecifictimeUsingPMUforceVDDMAXtotestedI/OpinMeasurecurrentFailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA0.0V-10nAPMUforceMeasureVss=0VDDmaxILOLVLSICoreOFFOFFPre-condition

Pattern1/0FailLT-4.5uA“0”Allinputpins=2.3VAlloutputpins=0V/2.3VDCTest–OutputLeakageHighTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditiontheDUTtotristatewithspecificpatternWaitaspecifictimeUsingPMUforceVDDMAXtotestedI/OpinMeasurecurrentFailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILOHVLSICoreAllinputpins=2.3VAlloutputpins=0V/2.3VOFFOFFPre-condition

Pattern1/0FailLT-4.5uA“1”DCTest–TestProgramConditionDCTest–IDDPurpose:IDD(orICC)measurescurrentofVddpinindifferentstates

Itmakessurepowerconsumptionnothigherthanexpected.FailureMode:WaferprocessissueAssemblyissueContactissue(VDD,VSS)DCTest–StaticIDDTestCondition:ProcedureUsingPMUtoapplyVDDmaxonVDDpinExecutePre-conditionpatternStopthepatternWaitaspecifictime

MeasurecurrentflowingintoVDDpinswhiledeviceisinidleFailIDDtestifthecurrentisgreaterthanIDDspec.(NormalinmA)PassFailGTspec2.0V10mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition

PatternDCTest–DynamicIDDTestCondition:ProcedureUsingPMUtoapplyVDDmaxonVDDpinExecutePre-conditionpatternWaitaspecifictime

MeasurecurrentflowingintoVDDpinswhiledeviceisexecutingpatternFailIDDtestifthecurrentisgreaterthanIDDspec.(NormalinmA)StoppatternPassFailGTspec2.0V80mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition

PatternPre-condition

PatternFunctionTest

ToverifyDRAMcanoperatefunctionally,weneedtodoFunctionaltest. -EasyFunctionTest(EFT)

ItcheckbasicICfunctionalitybyreading“0”(or“1”)fromall cellafterwriting“0”(or“1”)in. TypicalTestPattern:MarchPattern(e.g.MarchC-)

MarchC-

Algorithm: ↑(w0);↑(r0,w1);↑(r1,w0);↓(r0,w1);↓(r1,w0);↓(r0) OperationCount:10*n

Scantype:X-Scan(Xinc->Yinc),Y-Scan(Yinc->Xinc) FaultCoverage:MostofFailureMode0000000000000000000000000000000R0000000000000000W100000000000000R0100000000000000W110000000000000R0110000000000000W111000000000000R0111000000000000W1111000000001111111100001111111111111111111111111111DRAMTest–Pattern(X-scan)YX0001101100011011DRAMTest–MarchPatternDRAMTest–FailureModeStuck-atFault(SAF)CouplingFault(CF)ShortsbetweendatalinesCrosstalkbetweendatalinesTransistionFault(TF)Cellcanbesetto0andnotto1(orviceversa)whenit’soperatedAddressingFault(AF)AddresslinestuckOpeninaddresslineShortsbetweenaddresslinesWrongaccessCellstuckDriverstuckDatalinestuckNeighborPatternSensitiveFault(NPSF)PatternsensitiveinteractionbetweencellsDataRetentionFault(DRF)DatacannotkeptsamestatusincellastimepassDRAMTest–MarchPatternMarchC-isthemosteffectiveDRAMTest–1HTDefectModeOPENLEAKIDDEFTTESTERRELATED○○○○WAFERISSUE○○○○DIECRACK○○○DIECHIP○○○SURFACEDAMAGE○○NGDie○NONDIE