級計組實驗六報告

：一、實驗要實驗名簡單的類MIPS多周期流水化處理器實實驗目理解CPU的Pipeline，對DataHazardBranchHazard有初步認實驗范本次實驗將覆蓋以下范ISE的使使用VerilogHDL進行邏輯設(shè)計二、實驗原理由于前幾次已經(jīng)完成了CPU各部分的主要功能，因此只需要完成Top模塊修改Control模塊沒以及修改模塊間互聯(lián)的定義將單周期CPU進行分割，插入4級寄存器，將其分割為IF，ID，EX，M，WB五大部分：CTR模塊的修三、驗代inputCLOCK_IN;inputclock;inputinput[3:0]output[3:0]LED;outputreg[31:0]PC;wireassignclk=assignLED[3:0]=SWITCH[3:0];wire[4:0]OUT1;wire[31:0]OUT2;wire[31:0]OUT3;wire[3:0]ALU_CTR;//IFtoreg[31:0] [31:0]wire[31:0]//IDtoreg[31:0]reg[31:0]wire[31:0]reg[31:0]wire[31:0]reg[31:0]wire[31:0]reg[20:16]

reg[15:11]//toEXregID_EX_RegDst;wireID_EX_RegDst_;reg[1:0]wire[1:0]ID_EX_ALUOp_;regID_EX_ALUSrc;wire//toMEMControlregID_EX_Branch;wireID_EX_Branch_;regID_EX_MemWrite;wireID_EX_MemWrite_;regID_EX_MemRead;wireID_EX_MemRead_;//toWBregID_EX_RegWrite;wireID_EX_RegWrite_;regID_EX_MemtoReg;wireID_EX_MemtoReg_;//EXtoreg[31:0]EX_MEM_Add;regEX_MEM_Zero;wirereg[31:0]wire[31:0]reg[31:0]reg[5:0]//toMEMregEX_MEM_Branch;regEX_MEM_MemWrite;reg//tpWBregEX_MEM_RegWrite;regEX_MEM_MemtoReg;//MEMtoreg[31:0]reg[31:0]reg[4:0]//toWBregMEM_WB_RegWrite;regMEM_WB_MemtoReg;initialbeginPC=0;//IDtoEX//toEXCo=ntrol

//toMEMControl//tpWBControl//MEMtoWB//toWBControlalways@(negedgeclk)PC=(EX_MEM_Branch&inst_memalways@(negedgeclk)//toWBControl

always@(negedgeclk)IF_ID_PcAdd4=//EXtoMEM

always@(negedgeclk)ID_EX_PcAdd4=IF_ID_PcAdd4;

registeralways@(negedgeclk)

always@(negedgeclk) Ctrsignnext

assignOUT1=ID_EX_RegDstID_EX_InstLow:ID_EX_InstHigh;assignOUT2=ID_EX_ALUSrc?ID_EX_SignExt:ID_EX_ReadData2;always@(negedgeclk) EX_MEM_INST= ALUCtrAlualways@(negedgeclk) always@(n