課程計(jì)算機(jī)體系結(jié)構(gòu)實(shí)驗(yàn)exp1.basic knowledge

ComputerArchitectureExperiment浙江大學(xué)計(jì)算機(jī)學(xué)院Topic1.

BasicKnowledgeOutlineXilinxSpartan-3EStartKitBoardXilinxISE12.4orlaterXilinxSpartan-3EStartkitBoard（1）KeyFeaturesXilinxXC3S500ESpartan-3EFPGA2-line,16-characterLCDscreenEightdiscreteLEDsFourslideswitchesFourpush-buttonswitches50MHzclockoscillatorUSBCableforprogrammingFourslideswitchesFourpush-buttonswitchesEightdiscreteLEDs50MHzclockoscillator板上支持3個(gè)主時(shí)鐘輸入源：1）包括一個(gè)50MHz的時(shí)鐘晶振2)通過(guò)SMA連接器，時(shí)鐘可以板外供應(yīng)。反之，F(xiàn)PGA也可以提供時(shí)鐘信號(hào)或其它高速信號(hào)給SMA連接器3）分列式8-DIP時(shí)鐘晶振插槽CharacterLCDInterface4根LCD數(shù)據(jù)線與StrataFlash數(shù)據(jù)線SF_D<11:8>復(fù)用。LCD/StrataFlash存儲(chǔ)器依賴于設(shè)計(jì)而交互使用。當(dāng)存儲(chǔ)器失能時(shí)（SF_CE0=1）,FPGA用作全讀/寫通道給LCD。相反，當(dāng)LCD讀失能時(shí)（LCD_RW=0）,FPGA用作全讀/寫通道給存儲(chǔ)器。CharacterLCDInterfaceSignalOperationInitializingtheDisplayPower-OnInitializationDisplayConfigurationWritingDatatotheDisplayDisablingtheUnusedLCDXilinxISEExampleDesignaDisplayModule:ThefirstlineofLCDdisplays“*HelloWorld!*”.Accordingtotherotarypushbutton,thesecondlineofLCDWhensw[1:0]=00,itdisplays“REGS-xx”anditsvalue.Whensw[1:0]=01,itdisplaysfrom“IF-ADDR”to“RESERVE”anditsvalue.Whensw[1:0]=10,itdisplays“CP0S-xx”anditsvalue.Whensw[1:0]=11,itdisplays“RESERVE”anditsvalue.Step1:NewProjectStep2:DevicePropertiesStep3:CreateProjectCompletionStep4:NewVerilogModuleFile&UCFFileStep5:WriteVerilogHDLCode&UCFCodeSeedisplay.vclk_gen.vanti_jitter.vdisplcd.vmips_top.vdefine.vhmips_top.ucfStep6:EditConstraintsStep7:GenerateProgrammingFileSynthesi