計(jì)算機(jī)組成與結(jié)構(gòu)：chapter16 Control Unit Operation

ComputerOrganization&ArchitectureChapter16ControlUnitOperation16.1Micro-OperationsAcomputerexecutesaprograminmanyinstructioncycles,typically,

aninstruction/cycleFetch/executesub-cyclesEachsub-cyclehasanumberofstepsThesestepsarecalledmicro-operations,

seeFig.16.1Eachstepissimpleanddoesverylittle,atomicoperationofCPUMicro-operationsaretheatomicoperationsofaprocessorConstituentElementsofProgramExecutionFetchCycleAccessPC,PCcontainsaddressofnextinstructionAddressmovedtoMARAddressplacedonaddressbusControlunitrequestsmemoryreadResultplacedondatabus,copiedtoMBR

Then,toIRMBRisnowfreeforfurtherdatafetchesMeanwhilePCincrementedbyI(inparallelwithdatafetchfrommemory)FetchSequence(symbolic)t1: MAR(PC)t2: MBR(memory)

PC(PC)+It3: IR(MBR)(tx=timeunit/clockcycle,

aclockpulse)t1: MAR(PC)t2: MBR(memory)t3: PC(PC)+I

IR(MBR)SequenceofEvents,FetchCycle1RulesforClockCycleGroupingPropersequencemustbefollowedMAR(PC)mustprecedeMBR(memory)ConflictsmustbeavoidedCannotread&writesameregisteratsametimeMBR(memory)&IR(MBR)mustnotbeinsamecycleAlso:PC(PC)+IinvolvesadditionUseALUMayneedadditionalmicro-operationsIndirectCyclet1:MAR(IRaddress)-addressfieldofIRt2:MBR(memory)t3:IRaddress

(MBRaddress)MBRcontainsanaddressforoperandIRisnowinsamestateasifdirectaddressinghadbeenusedDataFlow--IndirectDiagramInterruptCyclet1: MBR(PC)t2: MARsave-address

PCroutine-addresst3: memory(MBR)ThisisaminimumMaybeadditionalmicro-opstogetaddressesNote,savingcontextisdonebyinterrupthandlerroutine,notmicro-opsExecuteCycleDifferentforeachinstructione.g.ADDR1,XaddthecontentsoflocationXtoRegister1,resultinR1t1: MAR(IRaddress)t2: MBR(memory)t3: R1R1+(MBR)ExecuteCycle(ISZ)ISZX-incrementandskipifzerot1: MAR(IRaddress)t2: MBR(memory)t3: MBR(MBR)+1t4: memory(MBR) if(MBR)==0thenPC(PC)+INotes:“ifclause”isasinglemicro-operationMicro-operationsdoneduringt4ExecutingCycle(BSA)BSAX-BranchandsaveaddressAddressofinstructionfollowingBSAissavedinXExecutioncontinuesfromX+IUsedforSubroutinecallt1:

MAR(IRaddress)

MBR(PC)t2:

memory(MBR)

PC(IRaddress)t3:

PC(PC)+IInstructionCycleEachphaseoftheinstructioncyclecanbedecomposedintoasequenceofelementarymicro-operationsInFig.16.3,anew2-bitregistercalledtheinstructioncyclecode(ICC)isassumedICC=00:fetch01:indirect10:execute11:interrupt16.2ControlofTheProcessorInordertodescribethecontrolunit,first,wemustknowbasicelementsofprocessormicro-operationsthatprocessorperformsfunctionsthatcontrolunitmustperformBasicElementsofProcessorALURegistersInternaldatapathsExternaldatapathsControlUnitTypesofMicro-operationDatatransferTransferdatabetweenregistersTransferdatafromregistertoexternalTransferdatafromexternaltoregisterPerformarithmeticorlogicalopsFunctionsofControlUnitSequencingThecontrolunitcausestheprocessortostepthroughaseriesofmicro-operationsinthepropersequenceExecutionThecontrolunitcauseseachmicro-operationtobeperformedThisisdonebyusingControlSignalsControlSignals

Controlsignals-inputClockOnemicro-instruction(orsetofparallelmicro-instructions)perclockpulseThisissometimesreferredtoastheprocessorcycletimeortheclockcycletimeInstructionregisterOp-codeofcurrentinstructionisusedtodetermineswhichmicro-instructionsareperformedFlagsBasedontheseflags,

controlunitdeterminesstateofCPUandResultsofpreviousoperationsControlsignalsfromcontrolbusInterruptsAcknowledgementsControlSignals-outputControlsignalstoCPUCausedatamovementfromoneregistertoanotherActivatespecificALUfunctionsControlsignalstocontrolbusControlsignalstomemoryControlsignalstoI/OmodulesModelofControlUnit

ExampleofControlSignalSequence-FetchMAR(PC)ControlunitactivatessignaltoopengatesbetweenPCandMAR,seefig.16.5,pp465MBR(memory)Simultaneously(t1,t2)t1:OpengatesbetweenMARandaddressbus(c0)Memoryreadcontrolsignalisonthecontrolbust2:OpengatesbetweendatabusandMBR,dataMBR(c5)ControlmakesPCadd1andstoretheresultbacktoPC(c3)AnotherControlSignalExampleFig.16.5isasimpleprocessorwithanaccumulatorWitheachclockpulse,thecontrolunitreadsallofitsinputsClockInstructionFlagsControlbusAndemitsasetofcontrolsignalsto:Datapaths:controlinternalflowofdataALU:controltheoperationofALUControlbusCausesmicro-operationstooccurTable16.1presentscontrolsignalsneededbysomemicro-opsDataPathsandControlSignalMicro-operationsandControlSignalsSeveralConclusionsontheControlUnitThecontrolunitistheenginethatrunstheentirecomputerItcontrolseverythingwithafewcontrolsSequencingmicro-opsExecutesomemicro-opsInternalProcessorOrganizationInCPU,

UsuallyasingleinternalbusexistsALUandregistersareconnected,seefig.16.6Simplifyinterconnection

&savespaceGatescontrolmovementofdataontoandoffthebusControlsignalscontroldatatransfertoandfromexternalsystemsbusTemporaryregistersmaybeneededforproperoperationofALU,

exceptforACInputregister:YTemporaryoutputregister:ZCPU

with

Internal

Bus16.3HardwiredImplementationImplementationofControlUnitImplementationmethodsofcontrolunitcanbeclassifiedintotwocategoriesHardwiredimplementationMicro-programmedimplementationInahardwiredimplementation,thecontrolunitisessentiallyacombinatorialcircuitMicro-programmedimplementationisthetopicofChapter17ControlunitinputsFlagsandcontrolbussignalsEachbitmeanssomething,

e.g.overflowInstructionregisterOp-codecausesdifferentcontrolsignalsforeachdifferentinstructionUniquelogicforeachop-codeDecodertakesencodedinputandproducessingleoutputadecoderhasnbinaryinputsand2noutputs,eachoutputactivesakindofcontrolsSeetable16.3ControlUnitwithDecodedInputsClockRepetitivesequenceofpulsesUsefulformeasuringdurationofmicro-opsMustbelongenoughtoallowsignalpropagationDifferentcontrolsignalsemittedatdifferenttimewithininstructioncycleNeedacounterwithdifferentcontrolsignalsfort1,t2etc.ControlUnitLogicOutputcontrolsignalisafunctionofinputcontrolsignalsSeeFig16.10Thisfunctioncanbeexpressed