CMOS超大規(guī)模集成電路設(shè)計經(jīng)典教材課件

1、Lecture 0: IntroductionLecture 0: Introduction0: Introduction2IntroductionIntegrated circuits: many transistors on one chip.Very Large Scale Integration (VLSI): bucketloads!Complementary Metal Oxide Semiconductor Fast, cheap, low power transistorsToday: How to build your own simple CMOS chipCMOS tra

2、nsistorsBuilding logic gates from transistorsTransistor layout and fabricationRest of the course: How to build a good CMOS chip0: Introduction2IntroductionIn0: Introduction3Silicon LatticeTransistors are built on a silicon substrateSilicon is a Group IV materialForms crystal lattice with bonds to fo

3、ur neighbors0: Introduction3Silicon Lattic0: Introduction4DopantsSilicon is a semiconductorPure silicon has no free carriers and conducts poorlyAdding dopants increases the conductivityGroup V: extra electron (n-type)Group III: missing electron, called hole (p-type)0: Introduction4DopantsSilicon0: I

4、ntroduction5p-n JunctionsA junction between p-type and n-type semiconductor forms a diode.Current flows only in one direction0: Introduction5p-n JunctionsA0: Introduction6nMOS TransistorFour terminals: gate, source, drain, bodyGate oxide body stack looks like a capacitorGate and body are conductorsS

5、iO2 (oxide) is a very good insulatorCalled metal oxide semiconductor (MOS) capacitorEven though gate is no longer made of metal0: Introduction6nMOS Transisto0: Introduction7nMOS OperationBody is usually tied to ground (0 V)When the gate is at a low voltage:P-type body is at low voltageSource-body an

6、d drain-body diodes are OFFNo current flows, transistor is OFF0: Introduction7nMOS Operation0: Introduction8nMOS Operation Cont.When the gate is at a high voltage:Positive charge on gate of MOS capacitorNegative charge attracted to bodyInverts a channel under gate to n-typeNow current can flow throu

7、gh n-type silicon from source through channel to drain, transistor is ON0: Introduction8nMOS Operation0: Introduction9pMOS TransistorSimilar, but doping and voltages reversedBody tied to high voltage (VDD)Gate low: transistor ONGate high: transistor OFFBubble indicates inverted behavior0: Introducti

8、on9pMOS Transisto0: Introduction10Power Supply VoltageGND = 0 VIn 1980s, VDD = 5VVDD has decreased in modern processesHigh VDD would damage modern tiny transistorsLower VDD saves powerVDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, 0: Introduction10Power Supply 0: Introduction11Transistors as SwitchesWe can vie

9、w MOS transistors as electrically controlled switchesVoltage at gate controls path from source to drain0: Introduction11Transistors a0: Introduction120CMOS InverterAY0110OFFON 1ONOFF0: Introduction120CMOS Inverte0: Introduction13CMOS NAND GateABY001011101110OFFOFFONON11OFFON OFFON01ON OFFONOFF10ON O

10、N OFFOFF000: Introduction13CMOS NAND Gat0: Introduction14CMOS NOR GateABY0010101001100: Introduction14CMOS NOR Gate0: Introduction153-input NAND GateY pulls low if ALL inputs are 1Y pulls high if ANY input is 00: Introduction153-input NAND 0: Introduction16CMOS FabricationCMOS transistors are fabric

11、ated on silicon waferLithography process similar to printing pressOn each step, different materials are deposited or etchedEasiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process0: Introduction16CMOS Fabricat0: Introduction17Inverter Cross-sectionTy

12、pically use p-type substrate for nMOS transistorsRequires n-well for body of pMOS transistors0: Introduction17Inverter Cros0: Introduction18Well and Substrate TapsSubstrate must be tied to GND and n-well to VDDMetal to lightly-doped semiconductor forms poor connection called Shottky DiodeUse heavily

13、 doped well and substrate contacts / taps0: Introduction18Well and Subs0: Introduction19Inverter Mask SetTransistors and wires are defined by masksCross-section taken along dashed line0: Introduction19Inverter Mask0: Introduction20Detailed Mask ViewsSix masksn-wellPolysiliconn+ diffusionp+ diffusion

14、ContactMetal0: Introduction20Detailed Mask0: Introduction21FabricationChips are built in huge factories called fabsContain clean rooms as large as football fieldsCourtesy of InternationalBusiness Machines Corporation. Unauthorized use not permitted.0: Introduction21FabricationCh0: Introduction22Fabr

15、ication StepsStart with blank waferBuild inverter from the bottom upFirst step will be to form the n-wellCover wafer with protective layer of SiO2 (oxide)Remove layer where n-well should be builtImplant or diffuse n dopants into exposed waferStrip off SiO20: Introduction22Fabrication S0: Introductio

16、n23OxidationGrow SiO2 on top of Si wafer900 1200 C with H2O or O2 in oxidation furnace0: Introduction23OxidationGrow0: Introduction24PhotoresistSpin on photoresistPhotoresist is a light-sensitive organic polymerSoftens where exposed to light0: Introduction24PhotoresistSp0: Introduction25LithographyE

17、xpose photoresist through n-well maskStrip off exposed photoresist0: Introduction25LithographyEx0: Introduction26EtchEtch oxide with hydrofluoric acid (HF)Seeps through skin and eats bone; nasty stuff!Only attacks oxide where resist has been exposed0: Introduction26EtchEtch oxid0: Introduction27Stri

18、p PhotoresistStrip off remaining photoresistUse mixture of acids called piranah etchNecessary so resist doesnt melt in next step0: Introduction27Strip Photore0: Introduction28n-welln-well is formed with diffusion or ion implantationDiffusionPlace wafer in furnace with arsenic gasHeat until As atoms

19、diffuse into exposed SiIon ImplanatationBlast wafer with beam of As ionsIons blocked by SiO2, only enter exposed Si0: Introduction28n-welln-well 0: Introduction29Strip OxideStrip off the remaining oxide using HFBack to bare wafer with n-wellSubsequent steps involve similar series of steps0: Introduc

20、tion29Strip OxideSt0: Introduction30PolysiliconDeposit very thin layer of gate oxide 20 (6-7 atomic layers)Chemical Vapor Deposition (CVD) of silicon layerPlace wafer in furnace with Silane gas (SiH4)Forms many small crystals called polysiliconHeavily doped to be good conductor0: Introduction30Polys

21、iliconDe0: Introduction31Polysilicon PatterningUse same lithography process to pattern polysilicon0: Introduction31Polysilicon P0: Introduction32Self-Aligned ProcessUse oxide and masking to expose where n+ dopants should be diffused or implantedN-diffusion forms nMOS source, drain, and n-well contac

22、t0: Introduction32Self-Aligned 0: Introduction33N-diffusionPattern oxide and form n+ regionsSelf-aligned process where gate blocks diffusionPolysilicon is better than metal for self-aligned gates because it doesnt melt during later processing0: Introduction33N-diffusionPa0: Introduction34N-diffusion

23、 cont.Historically dopants were diffusedUsually ion implantation todayBut regions are still called diffusion0: Introduction34N-diffusion c0: Introduction35N-diffusion cont.Strip off oxide to complete patterning step0: Introduction35N-diffusion c0: Introduction36P-DiffusionSimilar set of steps form p

24、+ diffusion regions for pMOS source and drain and substrate contact0: Introduction36P-DiffusionSi0: Introduction37ContactsNow we need to wire together the devicesCover chip with thick field oxideEtch oxide where contact cuts are needed0: Introduction37ContactsNow w0: Introduction38MetalizationSputte

25、r on aluminum over whole waferPattern to remove excess metal, leaving wires0: Introduction38MetalizationS0: Introduction39LayoutChips are specified with set of masksMinimum dimensions of masks determine transistor size (and hence speed, cost, and power)Feature size f = distance between source and drainSet by minimum width of polysiliconFeature size improves 30% every 3 years or soNormalize for feature size when describing design rulesExpress rules in terms of l = f/2E.g. l = 0.3 mm in 0.6 mm process0: Introduction39LayoutChips a0: Introduction40Simplified Design RulesC