2012-2013-2《數(shù)字邏輯設(shè)計(jì)及應(yīng)用》期末考試題-A參考解答

1、學(xué)期期 末 考試 A 卷_ 考試形式：30 一(3 10=3) 1 or high ). “dont-cares when designing a finite state machine, cost 0 or low 4 JQ+KQ 16 8 16 1101 The output voltage is 3.98 閉卷%， 期中二) approach. ) when counting to 0000 in decreasing order. ) bit at least. ). ) normal states at most, 4-bit Johnson counter with no ) n

2、ormal states, 4-bit linear feedback shift-register (LFSR) counter ) normal states. 4 bits, to construct a 4-bit binary code to gray ) will be the output. 學(xué)期期 末 考試 A 卷_ 考試形式：30 一(3 10=3) 1 or high ). “dont-cares when designing a finite state machine, cost 0 or low 4 JQ+KQ 16 8 16 1101 The output volt

3、age is 3.98 閉卷%， 期中二) approach. ) when counting to 0000 in decreasing order. ) bit at least. ). ) normal states at most, 4-bit Johnson counter with no ) normal states, 4-bit linear feedback shift-register (LFSR) counter ) normal states. 4 bits, to construct a 4-bit binary code to gray ) will be the

4、output. ) V when the input is 11111111. 考試日期：30 三20 13 年 07 月%， 實(shí)驗(yàn)四05 日0 五%， 期末六40 七% 八九十合計(jì)課程名稱： _數(shù)字邏輯設(shè)計(jì)及應(yīng)用考試時(shí)長： _120_分鐘課程成績構(gòu)成：平時(shí)本試卷試題由 _七_(dá)部分構(gòu)成，共 _7_頁。題號(hào)得分得 分I. Fill out your answers in the blanks 1. If a 74x138 binary decoder has 110 on its inputs CBA, the active LOW output Y5 should be ( 2. If the

5、 next state of the unused states are marked as this approach is called minimal ( 3.The RCO_L of 4-bit counter 74x169 is ( 4. To design a 001010 serial sequence generator by shift registers, the shift register should need ( 5. One state transition equation is Q*=JQ +KQ. If we use T flip-flop with ena

6、ble to complete the equation ，the enable input of T flip-flop should have the function EN=( 6. A 4-bit Binary counter can have ( self-correction can have ( with self-correction can have ( 7. If we use a ROM, whose capacity is 16 code converter, when the address inputs are 1001, ( 8. When the input i

7、s 10000000 of an 8 bit DAC, the corresponding output voltage is 2V. ( 得 分AGTBIN=0, D ). B) ALTBOUT=1, AEQBOUT=0, AGTBOUT=0 D) ALTBOUT=0, AEQBOUT=0, AGTBOUT=1 ) when A3A2A1A0=0100, B) C4=0, S3S2S1S0=0110 ) ). B) 65536 Which state in Figure 2 is ambiguous ( C ). B) B AEQBIN=0, C) C4=0, S3S2S1S0=1010 C

8、) 104 C) C and D A3A2A1A0=1101, D) 256 D) C II. Please select the only one correct answer in the following questions.(AGTBIN=0, D ). B) ALTBOUT=1, AEQBOUT=0, AGTBOUT=0 D) ALTBOUT=0, AEQBOUT=0, AGTBOUT=1 ) when A3A2A1A0=0100, B) C4=0, S3S2S1S0=0110 ) ). B) 65536 Which state in Figure 2 is ambiguous (

9、 C ). B) B AEQBIN=0, C) C4=0, S3S2S1S0=1010 C) 104 C) C and D A3A2A1A0=1101, D) 256 D) C 1. If a 74x85 magnitude comparator has ALTBIN=1, B3B2B1B0=0111 on its inputs, the outputs are ( A) ALTBOUT=0, AEQBOUT=0, AGTBOUT=0 C) ALTBOUT=1, AEQBOUT=0, AGTBOUT=1 2. As shown in Figure 1, what would the outpu

10、ts of the 4-bit adder 74x283 be ( B B3B2B1B0=1110 and S/A=1. A) C4=1, S3S2S1S0=0010 D) C4=0, S3S2S1S0=1110 Figure 1 3. Which of the following statements is INCORRECT? ( A A) A D latch is edge triggered and it will follow the input as long as the control input C is active low. B) A D flip flop is edg

11、e triggered and its output will not change until the edge of the controlling CLK signal. C) An S-R latch may go into metastable state if both S and R are changing from 11 to 00 simultaneously. D) The pulse applying to any input of an S -R latch must meet the minimum pulse width requirement. 4. The c

12、apacity of a memory that has 13 bits address bus and can store 8 bits at each address is ( B A) 8192 5. NOTA) A X+YW+Y1Analyze the sequential-circuit as showX+YW+Y1Analyze the sequential-circuit as shown D Flip-Flop with asynchronous 2Q1=00, complete the timing diagram for Q 2 1*= D *=D2)/Analyze th

13、e sequential-circuit as shown below, which contains two 74x163 4-bit binary BC1=Q2/， 2= Q1AXZYZZZDFigure 2得 分III. in Figure 3,preset and clear inputs. 15 1.Write out the excitation equations, transition equations and output equation. 5 2.Assume the initial state Q ,Q and Z. 10 Figure 3參考答案：激勵(lì)方程 : D1

14、=Q2/，D2= Q1 轉(zhuǎn)移方程： Q1 Q2輸出方程： Z= (CLK+Q參考評(píng)分標(biāo)準(zhǔn)：1. 5個(gè)方程正確得 5分；每錯(cuò)一個(gè)扣 1分，扣完 5分為止；2. Q1、Q2、Z的波形邊沿判斷正確，得 3分，錯(cuò)一個(gè)，扣 1分，扣完 3分為止；每個(gè)上升沿和下降沿各0.5分，錯(cuò) 1處扣 0.5分，扣完 7分為止。得 分IV. counter. 15 1 2.4 10, write out the state sequence for the circuit. 8Current state Next state LD_L ENT X 1 2.4 10, write out the state sequen

15、ce for the circuit. 8Current state Next state LD_L ENT X X 0 X 1 0 1 X 1 1 1 1 1 1 1 1 1 1 1 1 3/,CLR_L=(Q 5Q4Q3)/Design a sequence signal generator with self-correcting Outputs ENP QD QC QB QA QD* QC* QB* QA* X X X X X 0 0 0 0 X X X X X D C B A X X X X X QD QC QB QA 0 X X X X QD QC QB QA 1 0 0 0 0

16、0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 1 1 0 0 1 1 0 1 0 0 1 . . 1 1 1 1 1 0 0 0 0 to generate a serial output RCO 0 0 0 0 0 0 0 0 0 1 2. Assume the initial state is 33. Describe the modulus for the circuit. 3 The function table for 74x163 Inputs CLR_L 0 1 1 1 1 1 1 1 1 1 參考評(píng)分標(biāo)準(zhǔn)：1. LD_L=Q 4 2. 狀態(tài)

17、序列：十六進(jìn)制數(shù)表示： 03,08,13,18,23,28,33,38,03,08 或十進(jìn)制數(shù)表示： 3,8,19,24,35,40,51,56,3,88 錯(cuò) 1處扣 1分，扣完為止。3. m=24 3得 分V. sequence of 101100, using a 74x194 and a 74x151.15 1. List the transition table .4 2. Write out the canonical sum of feedback function LIN.4 Draw the circuit diagram.7Function 0 1 0 1 0=m(0,2,4

18、,5) Write out the state/output table for a Mealy machine that can detect the pattern 10101 or 10111 . QA QBDraw the circuit diagram.7Function 0 1 0 1 0=m(0,2,4,5) Write out the state/output table for a Mealy machine that can detect the pattern 10101 or 10111 . QA QB QC QD RIN QA QB QC QB QC QD LIN 1 4The function table for 74x194 Hold Shift right Shift left A B C D Load Iutputs Next state S1 S0 QA* QB* QC* QD* 0 0 1 參考評(píng)分標(biāo)準(zhǔn)：1. 轉(zhuǎn)移表正確 4分，錯(cuò) 1行扣 0.5 分。2. 反饋函數(shù)正確 LIN=D3. 電路圖正確 7分，錯(cuò) 1處扣 0.5分，扣完為止。得 分VI. The output Z=1 when the pattern is detected. Your mode