FPGA中用定制ROM產(chǎn)生正弦信號

1、FPGA中用定制ROM產(chǎn)生正弦信號簡介：本文詳細介紹了在fpga中定制ROM,以及用查表法產(chǎn)生正弦波的方法，并借助matlab加以驗證。編譯軟件用xilinx13.1.1.借助matlab生成ISE中ROM的.coe文件。在matlab工作區(qū)中輸入以下代碼。fid=fopen(sin.txt,a);str1=MEMORY_INITIALIZATION_RADIX=10;str2=MEMORY_INITIALIZATION_VECTOR=;fprintf(fid,t%snt%sn,str1,str2);fork=1:256;y(k)=sin(2*pi*k/256);y(k)=int8(y(k)*

2、100);fprintf(fid,t%4.0ft%cn,y(k),);endlileEditText21fclose(fid);在work文件夾下回生成一個sin.txt的文件，；打開ISE。2.在ISE中建立newproject添加新的verilogmodule文件，直接點next直MEMORY.MEMORYSelectSonrceTypeSelectsourcetypefileIP(COREGenerator&Arc!OjSchematiceJUserDocu/nent7VerilogModuleV1VerilogTestFixture10SelectSoxirceTypeSelectso

3、urcetypefil/.ImplementatimnConstrai丿J丿呂又攵:寸coe,IF(COREGenerator敕ArchitectujMEMFileSchematicUserDocumentVerilogModuleVerilogTestFixture；.:FIFOsMemoryInterfaceGenerators療RAM客&KOMsBlockMemoryDistributedMemoryGeiver0止-_%t%*E點擊next-finishMemoryTypeSinglePortROIZiDDRA3:D$BITERR-nDeiTERRROADDRECCpDRS7ACLKA

4、IWJECTSBITERRINJECTDBITERRDOUTA(15;DZiDDRA3:D$BITERR-nDeiTERRROADDRECCpDRS7ACLKAIWJECTSBITERRINJECTDBITERRDOUTA(15;DClockingOptionsCommonClockECCOptionsAlgorithmDefinesthealgorithmused1moreiriformation,BlockIcaoryGeneratorSimulaView：)Jmplementationo+yjpgmysiiuomHierarchy冋sinrom10 xc3sl00e-4cpl32(mys

5、inrom.v)I)BlockIcaoryGeneratorSimulaView：)Jmplementationo+yjpgmysiiuomHierarchy冋sinrom10 xc3sl00e-4cpl32(mysinrom.v)I)NoProcessesRunningOptionalOutputRegistersPortA匚RegisterPortAOutputProcesses：sinromBCOREGenerator斗ManageCoresRegenerat電Core.UpdateCoretoLatestVersii閆ViewHDLFunctionalModel冏ViewKDLInst

6、antiationTemp；JoelIPSymbolRegisterPortAOutputRegisterPortAinputADDRA70DOUTA|15:0)3930314142sinromyour_inst.(lka(clka)/inputc：/AdditionalCoinments:/zmodulecounter(en3930314142sinromyour_inst.(lka(clka)/inputc：/AdditionalCoinments:/zmodulecounter(enzell1-了relsec=0;endelsec=0;W%.1countercO(enzclkzacBeg

7、inCuthProcesses:mysinromoutmyromromO(,clka(elk)i/input.addrafaddra)/iiAlDesignSummary/ReportsDesignUtilitiesUserConstraints空dhw-芒-疫:工ViewRTLSchematicViewTechnologySchematicCheckSyntaxA*i4匕PA+VbA亡*.頂層示意圖以及內(nèi)部模塊連接*LUc(7;0加仿cOmysinrcDesignBehaviorH添加ITSelectSourceTypeSelectsourcetype,filen泗電anditslocati

8、on.Aksoci頂層示意圖以及內(nèi)部模塊連接*LUc(7;0加仿cOmysinrcDesignBehaviorH添加ITSelectSourceTypeSelectsourcetype,filen泗電anditslocation.AksociateSourceSelectasource時ithwhichtoassociatethenewsource.陽BMMFileChipScopeDefinitionandConnectionFile舉ImplementtionConstr亂int玄File“IF(COREGenerator&ArchitectureWizard)MEMFilemysiiuromcounterninrommysinroimysircounter添加代碼:noduletest;en(en)zel