常見面試筆試題

1、加減法moduleaddsub(input7:0dataa,input7:0datab,inputadd_sub,/ifthisis1,add;elsesubtractinputclk,outputreg8:0result);always(posedgeclk)beginif(add_sub)result=dataa+datab;/orassigncout,sum=dataa+datab;elseresult1101，然后和8，亦即1000相加就會得到5，亦即0101。至于溢出的最高位可以無視掉。乘法器modulemult(outcome,a,b);parameterSIZE=8;inputS

2、IZE:1a,b;outputreg2*SIZE:1outcome;integeri;always(aorb)beginoutcome=0;for(i=0,i=SIZE;i=i+1)if(bi)outcome=outcome+(a(i-1);endendmodule另一種乘法器。在初始化之際，取乘數(shù)和被乘數(shù)的正負關系，然后取被乘數(shù)和乘數(shù)的正值。輸出結果根據(jù)正負關系取得。elseif(Start_Sig)case(i)0:beginisNeg=Multiplicand人Multiplier7;Mcand=Multiplicand7?(Multiplicand+1b1):Multiplicand;

3、Mer=Multiplier7?(Multiplier+1b1):Multiplier;Temp=16d0;i=i+1b1;end1:/Multiplingif(Mer=0)i=i+1b1;elsebeginTemp=Temp+Mcand;Mer=Mer-1b1;end2:beginisDone=1b1;i=i+1b1;end3:beginisDone=1b0;i=2d0;endendcaseassignDone_Sig=isDone;assignProduct=isNeg?(Temp+1b1):Temp;endmodulebooth乘法器modulebooth_multiplier_modu

4、le(inputCLK,inputRSTn,inputStart_Sig,input7:0A,input7:0B,outputDone_Sig,output15:0Product,output7:0SQ_a,output7:0SQ_s,output16:0SQ_p);reg3:0i;reg7:0a;/resultofAreg7:0s;/reverseresultofAreg16:0p;/p空間，16+1位reg3:0X;/指示n次循環(huán)regisDone;always(posedgeCLKornegedgeRSTn)if(!RSTn)begini=4d0;a=8d0;s=8d0;p=17d0;X

5、=4d0;isDone=1b0;endelseif(Start_Sig)case(i)0:begina=A;s=(A+1b1);p=8d0,B,1b0;i=i+1b1;end1:if(X=8)beginX=4d0;i=i+4d2;endelseif(p1:0=2b01)beginp=p16:9+a,p8:0;i=i+1b1;endelseif(p1:0=2b10)beginp=p16:9+s,p8:0;i=i+1b1;endelsei=i+1b1;/00和11，無操作2:0or1.beginp=p16,p16:1;X=X+1b1;i=i-1b1;end/右移，最高位補3:beginisDone

6、=1b1;i=i+1b1;end4:beginisDone=1b0;i=4d0;endendcaseassignDone_Sig=isDone;assignProduct=p16:1;endmodule除法器moduledivider_module(inputCLK,inputRSTn,inputStart_Sig,input7:0Dividend,input7:0Divisor,outputDone_Sig,output7:0Quotient,output7:0Reminder,);reg3:0i;reg7:0Dend;reg7:0Dsor;reg7:0Q;reg7:0R;regisNeg;

7、regisDone;always(posedgeCLKornegedgeRSTn)if(!RSTn)begini=4d0;Dend=8d0;Dsor=8d0;Q=8d0;isNeg=1b0;isDone=1b0;endelseif(Start_Sig)case(i)0:beginDend=Dividend7?Dividend+1b1:Dividend;Dsor=Divisor7?Divisor:(Divisor+1b1);isNeg=Dividend7人Divisor7;iDend)beginQ=isNeg?(Q+1b1):Q;i=i+1b1;endelsebeginDend=Dend+Dso

8、r;Q=Q+1b1;end2:beginisDone=1b1;i=i+1b1;end3:beginisDone=1b0;ib)beginn=a-b;m=4b0001;state=S1;endelsebeginm=4b0000;n=a;state=b)beginm=m+1;n=n-b;state=S1;endelsebeginstate=S2;endendS2:beginresult=m;yu=n;state=S0;enddefule:state=S0;endcaseendendmodule13、一個可預置初值的7進制循環(huán)計數(shù)器verilogmodulecount(clk,reset,load,

9、date,out);inputload,clk,reset;input3:0date;outputreg3:0out;parameterWIDTH=4d7;always(clkorreset)beginif(reset)out=4d0;elseif(load)out=date;elseif(out=WIDTH-1)out=4d0;elseout=out+1;endendmoduleJohnson計數(shù)器約翰遜(Johnson)計數(shù)器又稱扭環(huán)計數(shù)器,是一種用n位觸發(fā)器來表示2n個狀態(tài)的計數(shù)器。它與環(huán)形計數(shù)器不同，后者用n位觸發(fā)器僅可表示n個狀態(tài)。n位二進制計數(shù)器(n為觸發(fā)器的個數(shù))有2切個狀態(tài)。若

10、以四位二進制計數(shù)器為例,它可表示16個狀態(tài)?！?000-1000-1100-1110-1111-0111-0011-0001-0000-1000”moduleJohnson(inputclk，inputclr，outputregN-1:0q);always(posedgeclkornegedgeclr)if(!clr)q=N1b0elseif(!q0)q=1b1，qN-1:1;elseq=1b0，qN-1:1;endmodule任意分頻，占空比不為50%always(clk)beginif(count=x-1)count=0;elsecount=count+1;endassignclkout=

11、county/y一般用count的最高位偶數(shù)分頻(8分頻，占空比50%)(計數(shù)至n-1，翻轉)modulecount5(reset，clk，out)inputclk，reset;outputout;reg1:0count;always(clk)if(reset)begincount=0;out=0;endelseif(count=3)begincount=0;out=!out:endelsecount=count+1;endmodule奇數(shù)分頻電路(占空比50%)。modulecount5(reset，clk，out)inputclk，reset;outputout;學習-好資料reg2:0m

12、,n;regcount1;regcount2;always(posedgeclk)beginif(reset)beginmv=0;count1=0;endelsebeginif(m=4)m=0;elsem=m+1;/“4”為分頻數(shù)NUM-1,NUM=5if(m2)count1=1;elsecount1=0;endendalways(negedgeclk)beginif(reset)beginn=0;count2=0;endelsebeginif(n=4)n=0;elsen=n+1;if(n2)count2=1;elsecount2=0;endendassignout=count1|count2

13、;半整數(shù)分頻圈98N-0.5T數(shù)分頻器旗理圖modulefdiv5_5(clkin,clr,clkout)inputclkin,clr;outputregclkout;regclkl;wireclk2;integercount;xorxor1(clk2,clkin,clk1)always(posedgeclkoutornegedgeclr)beginif(clr)beginclk1=1b0;endelseclk1=clk1;endalways(posedgeclk2ornegedgeclr)beginif(clr)begincount=0;clkout=1b0;endelseif(count=

14、5)begincount=0;clkout=1b1;endelsebegincount=count+1;clkout=1b0;endendendmodule小數(shù)分頻N=M/P.N為分配比，M為分頻器輸入脈沖數(shù)，P為分頻器輸出脈沖數(shù)N=(8X9+9X1)/(9+1)=8.1先做9次8分頻再做1次9分頻。modulefdiv8_1(clkin,rst,clkout)inputclkin,rst;outputregclkout;reg3:0cnt1,cnt2;always(posedgeclkinorposedgerst)beginif(rst)begincnt1=0;cnt2=0;clkout=0

15、;end08elseif(cnt19)/cnt1,beginif(cnt27)begincnt2=cnt2+1;clkout=0;endelsebegincnt2=0;cnt1=cnt1+1;clkout=1;endendelsebegin/cnt1,if(cnt28)begincnt2=cnt2+1;clkout=0;endelsebegincnt2=0;cnt1=0;clkout=1;endendendendmodule串并轉換modulep2s(clk,clr,load,pi,so)inputclk,clr,load;input3:0pi;outputso;reg3:0r;always(

16、posedgeclkornegedgeclr)if(clr)r=4h0;elseif(load)r=pi;elser=r,1b0;/orr1;assignso=r3;endmodulemodules2p(clk,clr,en,si,po)inputclk,clr,en,si;output3:0po;always(posedgeclkornegedgeclr)if(clr)r=8ho;elser=r,si;assignpo=(en)?r:4h0;endmoduleb)試用VHDL或VERILOG、ABLE描述8位D觸發(fā)器邏輯。moduledff(q,qn,d,clk,set,reset)inpu

17、t7:0d,set;inputclk,reset;outputreg7:0q,qn;always(posedgeclk)學習-好資料beginif(reset)beginqv=8hOO;qn=8hFF;endelseif(set)beginq=8hFF;qn=8hOO;endelsebeginq=d;qn=d;endendendmodule序列檢測“101”modulexulie101(clk,clr,x,z);inputclk,clr,x;outputregz;reg1:0state,next_state;parameters0=2b00,s1=2b01,s2=2b11,s3=2b10;al

18、ways(posedgeclkorposedgeclr)beginif(clr)state=s0;elsestate=next_state;endalways(stateorx)begincase(state)s0:beginif(x)next_state=s1;elsenext_state=s0;ends1:beginif(x)next_state=s1;elsenext_state=s2;ends2:beginif(x)next_state=s3;elsenext_state=s0;ends3:beginif(x)next_state=s1;elsenext_state=s2;enddef

19、ault:next_state=s0;endcaseendalways(state)begincase(state)s3:z=1;default:z=0;endcaseendendmodule按鍵消抖1.采用一個頻率較低的時鐘，對輸入進行采樣，消除抖動。moduleswitch(clk,keyin,keyout)parameterCOUNTWIDTH=8;inputclk,keyin;outputregkeyout;regCOUNTWIDTH-1:0counter;wireclk_use;/頻率較低的時鐘assignclk_use=counterCOUNTWIDTH-1;always(pose

20、gdeclk)counter=counter+1b1;always(posedgeclk_use)keyout=keyin;endmodule2.moduleswitch(clk,keyin,keyout)parameterCOUNTWIDTH=8;inputclk,keyin;outputregkeyout;regCOUNTWIDTH-1:0counter;initialcounter=0,keyout=0,keyin=0;always(posegdeclk)if(keyin=1)beginkey_m=keyin,counter=counter+1;endelsecounter=0;if(k

21、eyin&counterm)keyout=1;/m定義時延endmodule數(shù)碼管顯示modulenumber_mod_module/分別取得數(shù)字的十位和個位(CLK,RSTn,Number_Data,Ten_Data,One_Data);inputCLK;inputRSTn;input7:0Number_Data;output3:0Ten_Data;output3:0One_Data;reg31:0rTen;reg31:0rOne;always(posedgeCLKornegedgeRSTn)if(!RSTn)beginrTen=32d0;rOne=32d0;endelsebeginrTen

22、=Number_Data/10;rOne=Number_Data%10;endassignTen_Data=rTen3:0;assignOne_Data=rOne3:0;endmodulemoduleled(CLK,Ten_Data,One_Data,led0,led1);/數(shù)碼管顯示input3:0Ten_Data,One_Data;inputCLK;output7:0led0,led1;reg7:0led0,led1;always(posedgecp_50)begincasez(One_Data)4d0:led0=8b1100_0000;4d1:led0=8b1111_1001;4d2:l

23、ed0=8b1010_0100;4d3:led0=8b1011_0000;4d4:led0=8b1001_1001;4d5:led0=8b1001_0010;4d6:led0=8b1000_0010;4d7:led0=8b1111_1000;4d8:led0=8b1000_0000;4d9:led0=8b1001_0000;default:led0=8b1111_1111;endcasecasez(Ten_Data)4d0:led1=8b1100_0000;4d1:led1=8b1111_1001;4d2:led1=8b1010_0100;4d3:led1=8b1011_0000;4d4:le

24、d1=8b1001_1001;4d5:led1=8b1001_0010;4d6:led1=8b1000_0010;4d7:led1=8b1111_1000;4d8:led1=8b1000_0000;4d9:led1=8b1001_0000;default:led0=8b1111_1111;endcaseendendmodule5.fifo控制器.FIFO存儲器FIFO是英文FirstInFirstOut的縮寫，是一種先進先出的數(shù)據(jù)緩存器，他與普通存儲器的區(qū)別是沒有外部讀寫地址線，這樣使用起來非常簡單，但缺點就是只能順序寫入數(shù)據(jù)，順序的讀出數(shù)據(jù)，其數(shù)據(jù)地址由內部讀寫指針自動加1完成，不能像普通存

25、儲器那樣可以由地址線決定讀取或寫入某個指定的地址。在系統(tǒng)設計中，以增加數(shù)據(jù)傳輸率、處理大量數(shù)據(jù)流、匹配具有不同傳輸率的系統(tǒng)為目的而廣泛使用FIFO存儲器，從而提高了系統(tǒng)性能.FIFO參數(shù)：FIFO的寬度，thewidth，指FIFO一次讀寫操作的數(shù)據(jù)位；FIFO深度，THEDEEPTH，指FIFO可以存儲多少個N位的數(shù)據(jù)；滿標志，F(xiàn)IFO已滿或將要滿時送出的一個信號，以阻止FIFO的血操作繼續(xù)向FIFO中寫數(shù)據(jù)而造成溢出(overflow)；空標志，阻止FIFIO的讀操作；modulefifo_module(inputCLK,inputRSTn,inputWrite_Req,input7:0F

26、IFO_Write_Data,inputRead_Req,output7:0FIFO_Read_Data,outputFull_Sig,outputEmpty_Sig,/*/output7:0SQ_rS1,output7:0SQ_rS2,output7:0SQ_rS3,output7:0SQ_rS4,output2:0SQ_Count/*/);parameterDEEP=3d4;reg7:0rShiftDEEP:0;reg2:0Count;reg7:0Data;always(posedgeCLKornegedgeRSTn)if(!RSTn)beginrShift0=8d0;rShift1=8d

27、0;rShift2=8d0;rShift3=8d0;rShift4=8d0;Count=3d0;Data=8d0;endelseif(Read_Req&Write_Req&Count0)beginrShift1=FIFO_Write_Data;rShift2=rShift1;rShift3=rShift2;rShift4=rShift3;Data=rShiftCount;endelseif(Write_Req&CountDEEP)beginrShift1=FIFO_Write_Data;rShift2=rShift1;rShift3=rShift2;rShift4=rShift3;Count0

28、)beginData=rShiftCount;Count=Count-1b1;endassignFIFO_Read_Data=Data;assignFull_Sig=(Count=DEEP)?1b1:1b0;assignEmpty_Sig=(Count=0)?1b1:1b0;/*/assignSQ_rS1=rShift1;assignSQ_rS2=rShift2;assignSQ_rS3=rShift3;assignSQ_rS4=rShift4;assignSQ_Count=Count;/*Endmodulefifi2(指針控制)moduleFIFO(date,q,clr,clk,we,re,

29、ff,ef);parameterWIDTH=8,DEEPTH=8,ADDR=3;inputclk,clr;inputwe,re;inputWIDTH-1:0date;outputff,ef;outputregWIDTH-1:0q;regWIDTH-1:0mem_dateDEEPTH-1:0;regADDR-1:0waddr,raddr;regff,ef;always(posedgeclkornegedgeclr)/寫地址beginif(!clr)waddr=0;elseif(we=1&ff=0)waddr=waddr+1;elseif(we=1&ff=0&waddr=7)waddr=0;end

30、always(posedgeclk)beginif(we&!ff)mem_datewaddr=date;endalways(posedgeclkornegedgeclr)/讀地址beginif(!clr)raddr=0;elseif(re=1&ef=0)raddr=waddr+1;elseif(re=1&ef=0&raddr=7)raddr=0;endalways(posedgeclk)beginif(re&!ef)q=mem_dateraddr;endalways(posedgeclkornegedgeclr)beginif(!clr)ff=1b0;elseif(we&!re)&(waddr=raddr-1)|(waddr=DEEPTH-1)&(raddr=1b0)ff=1b1;elseff=1b0;endalways(posedgeclkornegedgeclr)beginif(!clr)ef=1b0;elseif(!we&re)&(waddr=raddr+1)|(raddr=DEEPTH-1)&(waddr=1b0)ef=