FPGA實驗8實驗八---用有限狀態(tài)機設(shè)計交通燈代碼

1、精選優(yōu)質(zhì)文檔-傾情為你奉上精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)專心-專注-專業(yè)精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)狀態(tài)機：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY xhd ISPort(clk : in std_logic; ra,rb,ya,yb,ga,gb : out std_logic );END xhd;Architecture a of xhd istype state is (S0,S1,S2,S3);signal presentstate,nextst

2、ate : state;signal tmp1,tmp2 : integer range 0 to 30;signal timeout1,timeout2: std_logic;signal q: std_logic_vector(21 downto 0);signal sec: std_logic;Begin-get 1 hz clock pulseprocess(clk)beginif clkevent and clk=1 then q=q+1; end if;sec=q(21); -get 1 hz clock pulseend process;timing: process(sec)b

3、eginif secevent and sec=1 then if tmp1=29 then timeout1=1; timeout2=0; tmp1=0; else if timeout1=1 then if tmp2=4 then timeout2=1; timeout1=0; tmp2=0; else tmp2=tmp2+1; end if; else tmp1 if timeout1=0 then nextstate=s0; ra=0; ya=0; ga=1; rb=1; yb=0; gb=0; else nextstate if timeout2=0 then nextstate=s

4、1; ra=0; ya=1; ga=0; rb=1; yb=0; gb=0; else nextstate if timeout1=0 then nextstate=s2; ra=1; ya=0; ga=1; rb=0; yb=0; gb=1; else nextstate if timeout2=0 then nextstate=s3; ra=1; ya=0; ga=0; rb=0; yb=1; gb=0; else nextstate nextstate=s0; timeout1=0; timeout20);Cy=0;Elsif CnEvent and Cn=1 thenIf En=1 t

5、henIf Cqi 1001 thenCqi :=Cqi+1; Cy=0; elsif cqi=1001then Cy0);end If;end If;end If;Dout0);CY=0;Elsif CLKEvent and CLK=1 thenIf EN=1 thenIf Cq 0101 thenCq :=Cq+1; CY=0; elsif cq=0101then CY0);end If;end If;end If;DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT=; END CASE; END PROCESS;END

6、behave;修改同上，編譯，封裝仿真波形如圖所示：分頻（1）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin isport ( CLK:in std_logic; FCLK:out std_logic);end fenpin;architecture bhv of fenpin is signal CK:std_logic; begin process(CLK) variable counter:integer

7、 range 0 to ; beginif(CLKEVENT AND CLK=1) THEN IF(counter=99999)THEN counter:=0;CK=NOT CK; ELSE counter:=counter+1; end if; end if; end process; FCLK=CK; end bhv;分頻（2）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin isport ( clk,clr:in std_logic; q:buffer std_logic);end fenpin;architecture b of fenpin is signal counter:integer range 0 to 49999; begin process(clr,clk) begin if(CLK=1 AND clkEVENT) THEN IF clr=1