集成電路設(shè)計(jì)-10-系統(tǒng)設(shè)計(jì)-3

1、EIS-Wuhan University1集成電路設(shè)計(jì)EIS-Wuhan University21.概述The Design Productivity ChallengeSource: sematech97A growing gap between design complexity and design productivity1981Logic Transistors per Chip (K)Productivity (Trans./Staff-Month)1983198519871989199119931995199719992001200320052007200958%/Yr. c o

2、 m pou ndComplex i t y gro wth r ate21%/Yr. c o m pou ndProduct i v i t y g rowth rate1981101001,00010,000100,0001,000,0 0 010,000, 0 0 01XXXXXXx1001,00010,000100,0001,000,0 0 010,000, 0 0 0100,000 , 0 0 0102.5m.35m.10m19831985198719891991199319951997199920012003200520072009Transis t o r / Sta ff Mo

3、 nthLogic T r a n s ist ors/C hipEIS-Wuhan University4A Simple ProcessorEIS-Wuhan University5A System-on-a-Chip: ExampleCourtesy: PhilipsEIS-Wuhan University6can be implemented with： 1. Hardware processor + suitable software programs (flexibility) a. Pentium IV + suitable software programs (high-lev

4、el language) b. TI-DSP + suitable software programs c. MCU(8051) + suitable software programs (low-level language)2. Dedicated hardware circuits (faster) a. old_PCBs (TTL SSI, MSI chips and wires) b. new_PCBs(some devices, application specific integrated circuit-ASIC, wires)3. Some hardware circuits

5、 + software programs (to solve more complex problems) a. System on a board (memory, processor, ASIC, I/O, other devices) b. System on a chip (SoC) current and future workHardware ImplementationMethods and Algorithms are used to solve some specific problems.memoryCPUASICI/ORISC-ARMPCIUSBUARTIEEE 1394

6、ASICEIS-Wuhan University7Hierarchical Components in PCB 1. Describe the circuits with Hardware Description Language (HDL)2. Synthesis the circuits . application specific integrated circuit(ASIC,IC or chip)EIS-Wuhan University8 Choose the design entry method: Schematic Gate level design Intuitive &am

7、p; easy to debugHDL (Hardware Description Language) Descriptive & portable Easy to modifyMixed HDL & SchematicDesign Entry for VLSI Systemalways (IN)begin OUT = (IN0 | IN1) & (IN2 | IN3);endEIS-Wuhan University9CustomStandard CellsCompiled CellsMacro CellsCell-based預(yù)擴(kuò)散Pre-diffused(Gate A

8、rrays)預(yù)布線Pre-wired(FPGAs)Array-based半定制SemicustomDigital Circuit Implementation ApproachesEIS-Wuhan University10The Custom Approach Intel 4004Courtesy IntelnNo CPLD or FPGA solutions;nAnalog circuits;nTo make system smaller;EIS-Wuhan University11Full Custom DesignCMOS Inverterinoutdone by chip desig

9、ner done by FabPacking, TestingmaskingEIS-Wuhan University12Transition to Automation and Regular StructuresEIS-Wuhan University13Semi Custom Designa. Product specificationb. Modeling with HDLc. Synthesis (by using suitable standard cell)d. Simulation and verification e. Physical placement and layout

10、f.Tape-out (real chip)g. Testing- implemented with suitable tools- implemented by suitable tools and mechanisms- implemented by suitable Fab companiesFPGA or CPLDReal ASIC chipless flexible, long design cycle, larger-scale production to reduce price more flexible, shorter design cycle, suitable for

11、smaller production Fab (TSMC, UMC, .)Two different solutions : Xilinx, AlteraEIS-Wuhan University143.基于單元的設(shè)計(jì)Cell-based Design (or standard cells)Routing channel requirements arereduced by presenceof more interconnectlayersFunctio n a lmodule(RAM,multipl i e r ,)RoutingchannelLogic c e l lFeedthr o u

12、 g h ce llRows of c e l lsEIS-Wuhan University15nCells are characterized and stored in librarynNeed update when technology advancenNeed technology mapping before layout for each designStandard CellsEIS-Wuhan University16Standard Cell ExampleBrodersen92EIS-Wuhan University17Standard Cell The New Gene

13、rationCell-structurehidden underinterconnect layersEIS-Wuhan University18Standard Cell - Example3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall timeEIS-Wuhan University19PLA- Programble Logic Arrayx0 x1x2ANDplanex0 x1x2Product termsORplanef0f1早期的設(shè)計(jì)自動(dòng)化結(jié)構(gòu)化設(shè)計(jì)EIS-Wuha

14、n University20Two-Level LogicInverting format (NOR-NOR) more effectiveEvery logic function can beexpressed in sum-of-productsformat (AND-OR)mintermEIS-Wuhan University21PLA Layout Exploiting Regularityf0f1x0 x0 x1x1x2x2Pull-up devicesPull-up devicesVDDGNDfAnd-PlaneOr-PlaneEIS-Wuhan University22Macro

15、ModulesEIS-Wuhan University23hard-macro Modules25632 (or 8192 bit) SRAMGenerated by hard-macro module generatorEIS-Wuhan University24“Soft” MacroModulesSynopsys DesignCompilerEIS-Wuhan University25Inside the 22v10 “Macrocell” BlocknOutputs may be registered or combinational, positive or inverted nRe

16、gistered output may be fed back to AND array for FSMs, etc. EIS-Wuhan University26Input/Output Equivalent SchematicsEIS-Wuhan University27“Intellectual Property”A Protocol Processor for WirelessEIS-Wuhan University284. Semicustom（半定制（半定制 ）Design FlowHDLLogic SynthesisFloorplanningPlacementRoutingTap

17、e-outCircuit ExtractionPre-Layout SimulationPost-Layout SimulationDesign CaptureEIS-Wuhan University29Courtesy SynopsysIterative Removal of Timing Violations (white lines)Design closure is the process by which a VLSI design is modified from its initial description to meet a growing list of design co

18、nstraints and objectives. EIS-Wuhan University30Integrating Synthesis with Physical DesignPhysical SynthesisRTL(Timing) ConstraintsPlace-and-RouteOptimizationNetlist with Place-and-Route InfoMacromodulesFixed netlistsEIS-Wuhan University31Pre-diffused(Gate Arrays)Pre-wired(FPGAs)Array-basedEIS-Wuhan

19、 University32預(yù)擴(kuò)散（掩模）陣列預(yù)擴(kuò)散（掩模）陣列Gate Array （ Sea-of-gates）rows ofcellsrouting channeluncommitted編程前編程前VDDGNDpolysiliconmetalpossiblecontact編程后編程后(4-input NOR)In 1In 2In 3In4OutEIS-Wuhan University33門海Sea-of-gateNMOSPMOSOxide-isolationPMOSNMOSNMOS幾何隔離幾何隔離oxide-isolation柵隔離柵隔離gate-isolation 無(wú)布線通道無(wú)布線通道P

20、rimitive CellsEIS-Wuhan University34Sea-of-gatesLSI Logic LEA300K(0.6 mm CMOS)EIS-Wuhan University35預(yù)布線陣列Prewired ArraysnBased on Programming Techniqueq熔絲Fuse-based (program-once)q非易失EPROM qRAM basednProgrammable Logic StyleqArray-Basedq查找表Look-up TablenProgrammable Interconnect StyleqChannel-routin

21、gqMesh networksEIS-Wuhan University36Fuse-Based FPGAantifuse polysiliconONO dielectric絕緣電介質(zhì)絕緣電介質(zhì)n+ antifuse diffusion2From Smith97Open by default, closed by applying current pulseEIS-Wuhan University37Programmable Array Logic (PAL) n any combinational logic can be realized as a sum-of-productsn PALs

22、 featurean array of AND-OR gates with programmable interconnectEIS-Wuhan University38I5I4O0I3I2I1I0O1O2O3Programmable AND arrayProgrammableOR arrayI5I4O0I3I2I1I0O1O2O3Programmable AND arrayFixed OR arrayO0I3I2I1I0O1O2O3Fixed AND arrayProgrammableOR arrayEIS-Wuhan University39Programming a PROMf01X2X

23、1X0f1NANA: programmed nodeEIS-Wuhan University40More Complex PALprogram m a b l e A ND ar ray (2i3jk)k macroc e l l sj -wide O R a rra yjmacroce l lproducttermsDQA1jBCLKOUTCii inputsi inputs, j minterms/macrocell, k macrocells2 i X j kEIS-Wuhan University41可編程ASIC的基本資源n位于芯片中央的可編程功能單元位于芯片中央的可編程功能單元n分

24、布于芯片各處的可編程布線分布于芯片各處的可編程布線n位于芯片四周的可編程位于芯片四周的可編程IO1.固定功能的功能單元固定功能的功能單元2.基于基于SRAM查找表結(jié)構(gòu)的功能單查找表結(jié)構(gòu)的功能單元元3.基于多路開(kāi)關(guān)結(jié)構(gòu)的功能單元基于多路開(kāi)關(guān)結(jié)構(gòu)的功能單元EIS-Wuhan University42Logic Cell of Actel Fuse-Based FPGAABSAY1CDSB1S0S11MUX as Function BlockF =AS +B SEIS-Wuhan University43Look-up Table Based Logic CellOutln1ln2MemoryIn

25、Out00000111011100功能為查找表的功能為查找表的SRAM構(gòu)成的函數(shù)發(fā)生器。構(gòu)成的函數(shù)發(fā)生器。EIS-Wuhan University44LUT-Based Logic CellCourtesy XilinxD4C1.C4xxxxxxD3D2D1F4F3F2F1LogicfunctionofxxxLogicfunctionofxxxLogicfunctionofxxxxxxx4xxxxxxxxxxxxxxxxxxxxxxxxxxxxxHPBitscontrolBitscontrolMultiplexer Controlledby Configuration Programxxxxx

26、xxxxxxxxxxxxxxxxxxxxxxxxxxxXilinx 4000 SeriesF Function.(4輸入查找表)2 bit 寄存器EIS-Wuhan University45Array-Based Programmable WiringInput/output pinProgrammed interconnectionInterconnectPointHorizontaltracksVertical tracksCellMEIS-Wuhan University46Mesh-based Interconnect NetworkCourtesy Dehon and WawrzyniekEIS-Wuhan University47Programming an AntifuseEIS-Wuhan University48EPLDMacrocellPrimary inputsEIS-Wuhan University49Altera MAXEIS-Wuhan University50Altera MAX Interconnect ArchitectureLAB2PIALAB1LAB6tPIAtPIArow channelcolumn channelLABCourtesy AlteraArray-based(MAX 3000-7000)Mesh-based(M