全自動(dòng)洗衣機(jī)控制系統(tǒng)設(shè)計(jì)文獻(xiàn)翻譯

1、AT89C51的概述1 AT89C51 應(yīng)用單片機(jī)廣泛應(yīng)用于商業(yè)：諸如調(diào)制解調(diào)器，電動(dòng)機(jī)控制系統(tǒng)，空調(diào)控制系統(tǒng)，汽車 發(fā)動(dòng)機(jī)和其他一些領(lǐng)域。這些單片機(jī)的高速處理速度和增強(qiáng)型外圍設(shè)備集合使得它們適 合于這種高速事件應(yīng)用場(chǎng)合。然而，這些關(guān)鍵應(yīng)用領(lǐng)域也要求這些單片機(jī)高度可靠。健 壯的測(cè)試環(huán)境和用于驗(yàn)證這些無論在元部件層次還是系統(tǒng)級(jí)別的單片機(jī)的合適的工具 環(huán)境保證了高可靠性和低市場(chǎng)風(fēng)險(xiǎn)。In tel平臺(tái)工程部門開發(fā)了一種面向?qū)ο蟮挠糜隍?yàn) 證它的AT89C51汽車單片機(jī)多線性測(cè)試環(huán)境。這種環(huán)境的目標(biāo)不僅是為 AT89C51汽車 單片機(jī)提供一種健壯測(cè)試環(huán)境，而且開發(fā)一種能夠容易擴(kuò)展并重復(fù)用來驗(yàn)證其他幾種將

2、 來的單片機(jī)。開發(fā)的這種環(huán)境連接了 AT89C51。本文討論了這種測(cè)試環(huán)境的設(shè)計(jì)和原理， 它的和各種硬件、軟件環(huán)境部件的交互性，以及如何使用AT89C51。1.1介紹8位AT89C51 CHMOS工藝單片機(jī)被設(shè)計(jì)用于處理高速計(jì)算和快速輸入/輸出。MCS51單片機(jī)典型的應(yīng)用是高速事件控制系統(tǒng)。商業(yè)應(yīng)用包括調(diào)制解調(diào)器，電動(dòng)機(jī)控 制系統(tǒng)，打印機(jī)，影印機(jī)，空調(diào)控制系統(tǒng)，磁盤驅(qū)動(dòng)器和醫(yī)療設(shè)備。汽車工業(yè)把MCS51單片機(jī)用于發(fā)動(dòng)機(jī)控制系統(tǒng)，懸掛系統(tǒng)和反鎖制動(dòng)系統(tǒng)。AT89C51尤其很好適用于得益于它的處理速度和增強(qiáng)型片上外圍功能集，諸如：汽車動(dòng)力控制，車輛動(dòng)態(tài)懸掛，反 鎖制動(dòng)和穩(wěn)定性控制應(yīng)用。由于這些決定

3、性應(yīng)用，市場(chǎng)需要一種可靠的具有低干擾潛伏 響應(yīng)的費(fèi)用-效能控制器，服務(wù)大量時(shí)間和事件驅(qū)動(dòng)的在實(shí)時(shí)應(yīng)用需要的集成外圍的能 力，具有在單一程序包中高出平均處理功率的中央處理器。擁有操作不可預(yù)測(cè)的設(shè)備的 經(jīng)濟(jì)和法律風(fēng)險(xiǎn)是很高的。一旦進(jìn)入市場(chǎng)，尤其任務(wù)決定性應(yīng)用諸如自動(dòng)駕駛儀或反鎖 制動(dòng)系統(tǒng)，錯(cuò)誤將是財(cái)力上所禁止的。重新設(shè)計(jì)的費(fèi)用可以高達(dá)500K美元，如果產(chǎn)品族享有同樣內(nèi)核或外圍設(shè)計(jì)缺陷的話，費(fèi)用會(huì)更高。另外，部件的替代品領(lǐng)域是極其昂 貴的，因?yàn)樵O(shè)備要用來把模塊典型地焊接成一個(gè)總體的價(jià)值比各個(gè)部件高幾倍。為了緩 和這些問題，在最壞的環(huán)境和電壓條件下對(duì)這些單片機(jī)進(jìn)行無論在部件級(jí)別還是系統(tǒng)級(jí) 別上的綜合測(cè)

4、試是必需的。In tel Cha ndler平臺(tái)工程組提供了各種單片機(jī)和處理器的系統(tǒng) 驗(yàn)證。這種系統(tǒng)的驗(yàn)證處理可以被分解為三個(gè)主要部分。系統(tǒng)的類型和應(yīng)用需求決定了 能夠在設(shè)備上執(zhí)行的測(cè)試類型。1.2 AT89C51提供以下標(biāo)準(zhǔn)功能4k字節(jié)FLASH閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM，32個(gè)I/O 口線，2個(gè)16位定 時(shí)/計(jì)數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電 路。同時(shí)，AT89C51降至OHz的靜態(tài)邏輯操作，并支持兩種可選的節(jié)電工作模式?？?閑方式體制CPU的工作，但允許 RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工 作。掉電方式保存RAM中的內(nèi)容，但振蕩器

5、體制工作并禁止其他所有不見工作直到下 一個(gè)硬件復(fù)位。£圖1 AT89C51方框圖1.3引腳功能說明Vcc :電源電壓GND:地P0 口： P0 口是一組8位漏極開路型雙向I/O 口，也即地址/數(shù)據(jù)總線復(fù)用。作為 輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫一1可作為高 阻抗輸入端用。在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。在Flash編程時(shí)，P0 口接受指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。P1 口： P1是一個(gè)帶內(nèi)部上拉電阻的 8位雙向I/O 口，P1的輸出緩沖級(jí)

6、可驅(qū)動(dòng) （吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫 一1,通過內(nèi)部的上拉電阻把端口 拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳 被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流 （IIL） o Flash編程和程序校驗(yàn)期間，P1接受低8位 地址。P2 口： P2是一個(gè)帶有內(nèi)部上拉電阻的 8位雙向I/O 口，P2的輸出緩沖級(jí)可驅(qū) 動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫一1,通過內(nèi)部的上拉電阻把端 口拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引 腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL ） o在訪問外部程序存儲(chǔ)器或 16位四肢的外 部

7、數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行 MOVX DPTR指令）時(shí)，P2 口送出高8位地址數(shù)據(jù)，在訪 問8位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX RI指令）時(shí)，P2 口線上的內(nèi)容（也 即特殊功能寄存器（SFR）區(qū)中R2寄存器的內(nèi)容），在整個(gè)訪問期間不改變。Flash編 程和程序校驗(yàn)時(shí)，P2也接收高位地址和其他控制信號(hào)。P3 口： P3是一個(gè)帶有內(nèi)部上拉電阻的 8位雙向I/O 口，P3的輸出緩沖級(jí)可驅(qū) 動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫一1,通過內(nèi)部的上拉電阻把端 口拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引 腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流 （IIL ）0 P3

8、 口還接收一些用于Flash閃速存儲(chǔ)器編 程和程序校驗(yàn)的控制信號(hào)。RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位ALE/PROG :當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE （地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE仍以時(shí)鐘振蕩頻率的 1/6輸出固定的正脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是，每 當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè) ALE脈沖。對(duì)Flash存儲(chǔ)器編程期間，該引腳還 用于輸入編程脈沖（PROG）。如有必要，可通過對(duì)特殊功能寄存器（SFR）區(qū)中的8EH 單元DO位置位，可禁止 ALE操作。該

9、位置位后，只有一條 MOVX和MOVC指令 ALE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無 效。PSEN:程序存儲(chǔ)允許輸出是外部程序存儲(chǔ)器的讀選通型號(hào)，當(dāng)89C51由外部存儲(chǔ) 器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次PSEN有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器，這兩次有效的 PSEN信號(hào)不出現(xiàn)。EA/VPP :外部訪問允許。欲使CPU僅訪問外部程序存儲(chǔ)器（地址0000HFFFFH）， EA端必須保持低電平（接地）。需注意的是：如果加密位 LB1被編程，復(fù)位時(shí)內(nèi)部會(huì) 鎖存EA端狀態(tài)。如EA端為高電平（接Vcc端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的 指

10、令。Flash存儲(chǔ)器編程時(shí)，該引腳加上+12v的編程允許電源Vpp，當(dāng)然這必須是該器 件使用12v編程電壓Vpp。XTAL1 :振蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。XTAL2 :振蕩器反相放大器的輸出端。89C51中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高 增益反相放大器，引腳 XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個(gè)放 大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體或陶瓷諧振器及電容 C1、C2接在放大器的反饋回路中構(gòu)成并聯(lián)振 蕩電路。對(duì)電容C1、C2雖沒有十分嚴(yán)格的要求，但電容容量的大小會(huì)輕微影響振蕩頻 率的高低、振蕩器工作的穩(wěn)定

11、性、起振的難易程度及溫度穩(wěn)定性，如果使用石英晶體， 我們推薦電容使用30Pf±0 Pf,而如使用陶瓷諧振器建議選擇 40Pf±0Pf。用戶也可以 采用外部時(shí)鐘。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端XTAL2則懸空。掉電模式：在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被 執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。推出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在Vcc恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時(shí)間以使振蕩 器重啟動(dòng)并穩(wěn)定工作。89C51的程

12、序存儲(chǔ)器陣列是采用字節(jié)寫入方式編程的，每次寫入 一個(gè)字符，要對(duì)整個(gè)芯片的EPROM程序存儲(chǔ)器寫入一個(gè)非空字節(jié)，必須使用片擦除的 方法將整個(gè)存儲(chǔ)器的內(nèi)容清楚。2編程方法編程前，設(shè)置好地址、數(shù)據(jù)及控制信號(hào)，編程單元的地址加在P1 口和P2 口的P2.0-P2.3（ 11位地址范圍為0000H0FFFH）,數(shù)據(jù)從P0 口輸入，引腳 P2.6、P2.7 和P3.6、P3.7的電平設(shè)置見表6, PSEB為低電平，RST保持高電平，EA/Vpp弓I腳是 編程電源的輸入端，按要求加上編程電壓，ALE/PROG引腳輸入編程脈沖（負(fù)脈沖）。編程時(shí)，可采用4 20MHz的時(shí)鐘振蕩器，89C51編程方法如下：在地址

13、線上加上要 編程單元的地址信號(hào)在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。激活相應(yīng)的控制信號(hào)。在高電 壓編程方式時(shí)，將 EA/Vpp端加上+12v編程電壓。每對(duì)Flash存儲(chǔ)陣列寫入一個(gè)字節(jié) 或每寫入一個(gè)程序加密位，加上一個(gè)ALE/PROG編程脈沖。改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)15步驟，知道全部文件編程結(jié)束。每個(gè)字節(jié)寫入周期是自身定時(shí)的， 通常約為1.5ms。數(shù)據(jù)查詢89C51單片機(jī)用數(shù)據(jù)查詢方式來檢測(cè)一個(gè)寫周期是否結(jié)束， 在一個(gè)寫周期中，如需要讀取最后寫入的那個(gè)字節(jié)，則讀出的數(shù)據(jù)的最高位（P0.7）是原來寫入字節(jié)的最高位的反碼。寫周期開始后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)查詢。2.1 Ready/Busy

14、字節(jié)編程的進(jìn)度可通過 Ready/Busy輸出信號(hào)檢測(cè)，編程期間，ALE變?yōu)楦唠娖揭籋| 后P3.4 （Ready/Busy）端被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，P3.4變 為高電平表示準(zhǔn)備就緒狀態(tài)。程序校驗(yàn)：如果加密位LB、LB2沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線 讀回原編寫的數(shù)據(jù)，采用下圖的電路，程序存儲(chǔ)器的地址由P1 口和P2 口的P2.0-P2.3 輸入，數(shù)據(jù)由P0 口讀出，P206、P2.7和P3.6、P3.7的控制信號(hào)見表6，PSEN保持低 電平，ALE、EA和RST保持高電平。校驗(yàn)時(shí)，P0 口必須接上10k左右的上拉電阻。ADWOOCXihWFFFH- A1

15、1SEC FlASHPR9M刪I4_MX-ES TADLE924 MH£二P1%R2 0 P2.3 P0P2JBP2 7ALEP3J8P3 7JCWL2EAXWL1RSTPSEN圖2編程電路2+iXO；+i>FFFH阿-A11»St E FU$HPR>.GfiM4JlNG-WX-ES TABLE珍 Mtt X口匚PIVKP2.0 -P2.3 因P2.6P2 74LEP9.SP3.7WTBI <5r j.A IRuRSTPSEtinirttiGND圖3校驗(yàn)電路側(cè) DAT* f |U$E IC'KPULLJUPSj2.2芯片擦除利用控制信號(hào)的正確組合(

16、表6)并保持ALE/PROG引腳10ms的低電平脈沖寬度即 可將EPROM陣列(4k字節(jié))和三個(gè)加密位整片擦除，代碼陣列在片擦除操作中將任何非 空單元寫入II 1這步驟需在編程之前進(jìn)行。2.3讀片內(nèi)簽名字節(jié)89C51單片機(jī)內(nèi)有3個(gè)簽名字節(jié),地址為030H、031H和032H。于聲明該器件的 廠商、號(hào)和編程電壓。讀簽名字節(jié)的過程和單元030H、031H和032H的正常校驗(yàn)相仿, 只需要將P3.6和P3.7保持低電平，返回值意義如下：(030H) = 1EH聲明產(chǎn)品由ATMEL公司制造(031H) = 51H聲明為89C51單片機(jī)。(032H) = FFH聲明為12V編程電壓。(032H) = 0

17、5H聲明為5編程電壓。2.4編程接口采用控制信號(hào)的正確組合可對(duì) Flash閃速存儲(chǔ)陣列中的每一代碼字節(jié)進(jìn)行寫入和存儲(chǔ)器的整片擦除，寫操作周期是自身定時(shí)的，初始化后它將自動(dòng)定時(shí)到操作完成。微機(jī) 接口實(shí)現(xiàn)兩種信息形式的交換。在計(jì)算機(jī)之外，由電子系統(tǒng)所處理的信息以一種物理信 號(hào)形式存在，但在程序中，它是用數(shù)字表示的。任一接口的功能都可分為以某種形式進(jìn) 行數(shù)據(jù)庫變換的一些操作，所以外部和內(nèi)部形式的轉(zhuǎn)換是由許多步驟完成的。模擬-數(shù)字轉(zhuǎn)換器（ADC ）用來將連續(xù)變化信號(hào)變成相應(yīng)的數(shù)字量，這數(shù)字量可是可能性的二進(jìn) 制數(shù)值中的一固定值。如果傳感器輸出不是連續(xù)變化的，就不需模擬-數(shù)字轉(zhuǎn)換。這種情況下，信號(hào)調(diào)理單

18、元必須將輸入信號(hào)變換成為另一信號(hào)，也可直接與接口的下一部分，即微計(jì)算機(jī)本身的輸入輸出單元相連接。輸出接口采用相似的形式，明顯的差別在于信 息流的方向相反；是從程序到外部世界。這種情況下，程序可稱為輸出程序，它監(jiān)督接 口的操作并完成數(shù)字-模擬轉(zhuǎn)換器（DAC ）所需數(shù)字的標(biāo)定。該子程序依次送出信息給 輸出器件，產(chǎn)生相應(yīng)的電信號(hào)，由 DAC轉(zhuǎn)換成模擬形式。最后，信號(hào)經(jīng)調(diào)理（通常是 放大）以形成適應(yīng)于執(zhí)行器操作的形式。在微機(jī)電路中使用的信號(hào)幾乎總是太小而不能 被直接地連到¥卜部世界II,因而必須用某種形式將其轉(zhuǎn)換成更適宜的形式。接口電路部 分的設(shè)計(jì)是使用微機(jī)的工程師所面臨最重要的任務(wù)之一。我

19、們已經(jīng)了解到微機(jī)中，信號(hào) 以離散的位形式表示。當(dāng)微機(jī)要與只有打開或關(guān)閉操作的設(shè)備相連時(shí)，這種數(shù)字形式是 最有用的，這里每一位都可表示一開關(guān)或執(zhí)行器的狀態(tài)。為了解決實(shí)際問題，一個(gè)單片 機(jī)不僅包括CPU,程序和數(shù)據(jù)存儲(chǔ)器，另外，它必須含有通過 CPU訪問外部信息的硬 件。一旦CPU收集到數(shù)據(jù)信息和流程，它必須能夠改變外部領(lǐng)域的一部分，這些硬件 設(shè)備稱作外圍設(shè)備，它們是 CPU通往外部的窗口。單片機(jī)可利用外圍設(shè)備中最基本的用于一般用途的I/O接口，每個(gè)I/O接口既可作為輸入端又可作為輸出端，每個(gè)I/O接口的功能取決與程序初始化階段對(duì)數(shù)據(jù)方位寄存 器相應(yīng)位進(jìn)行置一和清零操作，通過 CPU指令對(duì)數(shù)據(jù)寄存

20、器相應(yīng)位進(jìn)行置一和清零來 置一和清零輸出端口，同樣輸入端口邏輯位也可以通過CPU指令訪問。一些類型的串行口單元允許CPU與外部設(shè)備進(jìn)行串口通信，用串口位代替平行位進(jìn)行通信需要少許 的I/O 口，這樣使通信費(fèi)用降低但速度也相對(duì)慢些。串口傳送可以同步也可以異步。來源于：AT89C51的概況附：英文原文The General Situation of AT89C511 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-c

21、o ntrol systems, air con diti oner con trol systems, automotive engine and among others. The high process ing speed and enhan ced peripheral set of these microc on trollers make them suitable for such high-speed event-based applications. However, these critical application doma ins also require that

22、 these microc on trollers are highly reliable. The high reliability and low market risks can be en sured by a robust testi ng process and a proper tools en vir onment for the validati on of these microc on trollers both at the comp onent and at the system level. In tel Plaform Engin eeri ng departme

23、 nt developed an object-orie nted multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microc on trollers, but to develop an en vir onment which can

24、be easily exte nded and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software

25、 en vir onmen tal comp onen ts, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microco ntrollers are desig ned to han dle high-speedcalculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed eve nt con trol systems. Commercial applicati o

26、ns in clude modems,motor-c on trol systems, prin ters, photocopiers, air con diti oner con trol systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers in engin e-c on trol systems, airbags, suspe nsion systems, and an tilock brak ing systems (ABS). The AT89

27、C51 is especially well suited to applicati ons that ben efit from its process ing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dyn amic suspe nsion, an tilock brak ing, and stability con trol applicatio ns. Because of these critical application

28、s, the market requires a reliable cost-effective controller with a low in terrupt late ncy resp on se, ability to service the high nu mber of time and eve nt drive n integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financ

29、ial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means

30、2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the comp onent. To mitigate these problem

31、s, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage con diti on s.This complete and thorough validati on n ecessitates not only a well-defi ned process but also a proper environment an

32、d tools to facilitate and execute the mission successfully.Intel Chan dler Platform Engin eeri ng group provides post silic on system validati on (SV) of various micro-co ntrollers and processors. The system validatio n process can be broke n in to three major parts.The type of the device and its ap

33、plicati on requireme nts determ ine which types of testi ng are performed on the device.1.2 The AT89C51 provides the following standard features4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-ch

34、ip oscillator and clock circuitry .In additi on, the AT89C51 is desig ned with static logic for operati on dow n to zero freque ncy and supports two software selectable power sav ing modes. The Idle Mode stops the CPU while allowi ng the RAM, timer/c oun ters,serial port and in terrupt sys -tem to c

35、ontinue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -atordisabling all other chip functions until the next hardware reset.呷 4 > pcltFigure 1 Block Diagram1.3Pin DescriptionVCC Supply voltage.GND Grou nd.Port 0: Port 0 is an 8-bit open-drain bi-directional I/O por

36、t. As an output port, each pin cansink eight TTL in puts. When 1s are writte n to port 0 pins, the pins can be used as highimpeda nce in puts.Port 0 may also be con figured to be the multiplexed loworder address/data busduri ng accesses to exter nal program and data memory. I n this mode P0 has in t

37、ernalpullups.Port 0 also receives the code bytes duri ng Flash program min g,a nd outputs the codebytes duri ng program verificati on.Exter nalpullups are required duri ngprogramverificati on.Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/

38、so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 1 pins that are externally being pulled low will source current (IIL) becauseof the internal pullups.Port 1 also receives the low-order address bytes

39、duri ng Flash program ming and verificati on.Port 2： Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as in puts. As in puts, Port 2

40、 pins that are exter nally being pulled low will source curre nt (IIL) because of the internal pullups. Port 2 emits the high-order address byte duri ng fetches from exter nal program memory and duri ng accesses to Port 2 pi ns that are externally being pulled low will source curre nt (IIL) because

41、of the internal pullups.Port 2 emits the high-order address byte duri ng fetches from exter nal program memory and during accessesto external data memory that use 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data mem

42、ory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Fun cti on Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port

43、 3 outputbuffers can sin k/sou -rce four TTL in puts.Whe n 1s are writte n to Port 3 pi ns they are pulled high by the internal pullups and can be used as in puts. As in puts,Port 3 pins that are exter nally being pulled low will source curre nt (IIL) because of the pullups.Port 3 also serves the fu

44、nctions of various special featuresof the AT89C51 as listed below:RST: Reset in put. A high on this pin for two mach ine cycles while the oscillator is running resets the device.ALE/PROG : Address Latch Enable output pulse for latching the low byte of the address duri ngaccesses to exter nal memory.

45、This pin is also the program pulse in put (PROG) duri ng Flash programmingn normal operation ALE is emitted at a constant rate of 1/6 the oscillator freque ncy,a nd may be used for exter nal tim ing or clock ing purposes. Note, however, that one ALEpulse is skipped duri -ng each access to external D

46、ataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN

47、： Program Store Enable is the read strobe to external program memory. When theAT89C51 is executi ng code from exter nal program memory, PSEN is activated twiceeach mach ine cycle, except that two PSEN activati ons are skipped duri ng each access toexter nal data memory.EA/VPP : External Access Enabl

48、e. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be intern ally latched on reset.EA should be strapped to VCC for internal program executio ns. This p

49、in alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.XTAL1 : In put to the inverting oscillator amplifier and in put to the internal clock operat in gcircuit.XTAL2 : Output from the in vert ing oscillator amplifier.Oscillator Charact

50、eristicsXTAL1 and XTAL2 are the in put and output, respectively, of an inverting amplifierwhich can be con figured for use as an on-chip oscillator, as show n in Figure 1. Either aquartz crystal or ceramic res on ator may be used. To drive the device from an exter nalclock source, XTAL2 should be le

51、ft unconnected while XTAL1 is driven as shown in Figure 2.There are no requireme nts on the duty cycle of the external clock sig nal, since the in put to the in ternal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be ob

52、served. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remai n active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers rema in un cha nged during this mode. The idle mode can be terminated by any enabled

53、interrupt or by a hardware reset. It should be no ted that whe n idle is termi nated by a hard ware reset, the device no rmally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal

54、RAM in this eve nt, but access to the port pins is not in hibited. To elim in ate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down Mo

55、de : In the power-down mode, the oscillator is stopped, and the in structi on that inv okes power-dow n is the last in structio n executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-dow n is a hardware reset.

56、Reset redefi nes the SFRs but does not cha nge the on-chip RAM. The reset should not be activated before VCC is restored to its normal operati ng level and must be held active long eno ugh to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed byte-bybyte in eit

57、her programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore program ming the AT89C51, the address, data and con trol sig nals should be set up accord ing to the Flash program ming mode table

58、and Figure 3 and Figure 4. To program the AT89C51, take the followi ng steps.1. In put the desired memory locati on on the address lin es.2. In put the appropriate data byte on the data lin es. 3. Activate the correct comb in ati on of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more tha n 1.5 ms. Repeat steps 1 through