[信息與通信]基于VHDL的數(shù)字邏輯設(shè)計ppt課件

1、基于基于VHDL的數(shù)字邏輯設(shè)計的數(shù)字邏輯設(shè)計n 常用組合邏輯電路設(shè)計常用組合邏輯電路設(shè)計n 常用時序邏輯電路設(shè)計常用時序邏輯電路設(shè)計n VHDLVHDL程序設(shè)計規(guī)范程序設(shè)計規(guī)范組合邏輯電路設(shè)計1.1.分析邏輯問題，抽象輸入、輸出邏輯變量。分析邏輯問題，抽象輸入、輸出邏輯變量。2.2.列真值表、寫函數(shù)表達(dá)式。列真值表、寫函數(shù)表達(dá)式。3.3.采用基本門電路、采用基本門電路、PLDPLD實現(xiàn)。實現(xiàn)。實體描述ENTITY _entity_name ISISPORT(_input_name: INSTD_LOGIC;_input_vector_name : IN STD_LOGIC_VECTOR (_h

2、igh downto _low);_output_name, : OUT STD_LOGIC);_output_vector_name : OUT STD_LOGIC_VECTOR (_high downto _low);END _entity_name;結(jié)構(gòu)體描述ARCHITECTURE a OF _entity_name ISSIGNAL _signal_name : STD_LOGIC;BEGIN- Process Statement- Concurrent Procedure Call- Concurrent Signal Assignment- Conditional Signal

3、Assignment- Selected Signal Assignment- Component Instantiation Statement- Generate StatementEND a;一、常用組合邏輯電路設(shè)計一、常用組合邏輯電路設(shè)計（1）編碼器）編碼器（2）譯碼器）譯碼器 （3）比較器）比較器 （4）數(shù)據(jù)選擇器）數(shù)據(jù)選擇器 （5）三態(tài)輸出電路）三態(tài)輸出電路 （1）編碼器A6A7A5A4A3A2A1A0Y2Y1Y083編碼器編碼器ENA7 A6 A5 A4 A3 A2 A1 A0Y2 Y1 Y000000001000000000100010000010001000001000011

4、00010000100001000001010100000011010000000111library ieee;use ieee.std_logic_1164.all;entity bmq isport( A : in std_logic_vector(7 downto 0); En : in std_logic; Y : out std_logic_vector(2 downto 0);end bmq;architecture m1 of bmq issignal sel : std_logic_vector(8 downto 0);beginsel=En & A;with sel

5、 select Y= 000 when 100000001, 001 when 100000010, 010 when 100000100, 011 when 100001000, 100 when 100010000, 101 when 100100000, 110 when 101000000, 111 when 110000000, 000 when others; end m1;architecturearchitecture m2 m2 ofof bmq bmq isissignalsignal sel : std_logic_vector(8 downto 0); sel : st

6、d_logic_vector(8 downto 0);beginbeginProcessProcess(En, A)(En, A)BeginBeginIf If En=1 En=1 thenthen if if A= 00000001 A= 00000001 then then Y= 000; Y= 000; elsifelsif A= 00000010 A= 00000010 thenthen Y= 001; Y= 001; elsifelsif A= 00000100 A= 00000100 thenthen Y= 010; Y= 010; elsifelsif A= 00001000 A

7、= 00001000 thenthen Y= 011; Y= 011; elsifelsif A= 00010000 A= 00010000 then then Y= 100; Y= 100; elsifelsif A= 00100000 A= 00100000 thenthen Y= 101; Y= 101; elsifelsif A= 01000000 A= 01000000 thenthen Y= 110; Y= 110; else else Y= 111; Y= 111; end ifend if; ;ElseElse Y= 000; Y= 000; end ifend if; ;en

8、d processend process; ;endend m2; m2;（2）譯碼器A. 38譯碼器38譯碼器譯碼器A6A7A5A4A3A2A1A0Y2Y1Y0ENlibrarylibrary ieee; ieee;useuse ieee.std_logic_1164.all; ieee.std_logic_1164.all;entityentity ymq ymq isisportport( ( Y : in std_logic_vector(2 downto Y : in std_logic_vector(2 downto 0);0); EN : in std_logic; EN : i

9、n std_logic; A : out std_logic_vector(7 downto A : out std_logic_vector(7 downto 0);0);endend ymq; ymq;architecturearchitecture m1 m1 ofof ymq ymq isissignalsignal sel : std_logic_vector(3 downto 0); sel : std_logic_vector(3 downto 0);beginbeginsel=En & Y;sel=En & Y;withwith sel sel selectse

10、lect A=00000001 A=00000001 whenwhen 1000, 1000, 00000010 00000010 whenwhen 1001, 1001, 00000100 00000100 whenwhen 1010, 1010, 00001000 00001000 when when 1011, 1011, 00010000 00010000 whenwhen 1100, 1100, 00100000 00100000 whenwhen 1101, 1101, 01000000 01000000 whenwhen 1110, 1110, 10000000 10000000

11、 whenwhen 1111, 1111, 11111111 11111111 whenwhen others; others; end end m1; m1; （2）譯碼器B.碼制轉(zhuǎn)換四位二進(jìn)制碼轉(zhuǎn)換為四位二進(jìn)制碼轉(zhuǎn)換為BCD碼，并譯碼顯示。碼，并譯碼顯示。（數(shù)碼管為共陰極）（數(shù)碼管為共陰極）LibraryLibrary ieee; ieee;UseUse ieee.std_logic_1164.all; ieee.std_logic_1164.all;UseUse ieee.std_logic_unsigned.all; ieee.std_logic_unsigned.all;Entity

12、Entity bcd bcd isisPortPort( ( A : A : inin std_logic_vector(3 downto 0); std_logic_vector(3 downto 0);bcd0,bcd1 : bcd0,bcd1 : outout std_logic_vector(3 std_logic_vector(3 downto 0);downto 0);seven0,seven1 : seven0,seven1 : outout std_logic_vector(6 std_logic_vector(6 downto 0)downto 0););EndEnd bcd

13、; bcd;ArchitectureArchitecture a a ofof bcd bcd isis signalsignal tmp: tmp:std_logic_vectorstd_logic_vector(3 (3 downto 0);downto 0);BeginBegin bcd0=A bcd0=A whenwhen (A10) (A10) elseelse A+6; A+6; bcd1=“0000” bcd1=“0000” whenwhen (A10) (A10) elseelse “0001”;“0001”; tmp = bcd0; tmp = bcd0; seven0=01

14、11111 seven0=0111111 whenwhen tmp=0000 tmp=0000 elseelse -0-0 0000110 0000110 whenwhen tmp=0001 tmp=0001 elseelse -1-1 1011011 1011011 whenwhen tmp=0010 tmp=0010 elseelse -2-2 1001111 1001111 whenwhen tmp=0011 tmp=0011 elseelse -3-3 1100110 1100110 whenwhen tmp=0100 tmp=0100 elseelse -4-4 1101101 11

15、01101 whenwhen tmp=0101 tmp=0101 elseelse -5-5 1111101 1111101 whenwhen tmp=0110 tmp=0110 elseelse -6-6 0000111 0000111 whenwhen tmp=0111 tmp=0111 elseelse -7-7 1111111 1111111 whenwhen tmp=1000 tmp=1000 elseelse -8-8 1101111 1101111 whenwhen tmp=1001 tmp=1001 elseelse -9-9 0000000 ;0000000 ;seven1=

16、“0111111” seven1=“0111111” whenwhen (A10) (Ab， 輸出為：輸出為：agtb=1， altb= 0 ， aeqb=0;如果如果 ab， 輸出為：輸出為：altb=1， agtb= 0 ， aeqb=0;如果如果 a=b， 輸出為：輸出為：aeqb=1， agtb= 0 ， altb=0。Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;ENTITY cmpab IS PORT (A, B :in std_logic_vector(7 downto 0); A

17、GTB, ALTB, AEQB : out std_logic);END cmpab;ARCHITECTURE a OF cmpab ISBEGIN aeqb=1 when a=b else 0; agtbb else 0; altb=1 when aB then agtb=1; elsif A=B then aeqb=1; else altb=1; end if; end process; END b;（4）數(shù)據(jù)選擇器4選1 MUX ABCDYS0S1library ieee;use ieee.std_logic_1164.all;entity mux41 is port(A,B,C,D:

18、in std_logic; sel : in std_logic_vector(1 downto 0); dout : out std_logic);end mux41;architecture archmux of mux41 is begin with sel select dout=A when 00, B when 01, C when 10, D when others;end archmux; （5）三態(tài)輸出電路 AENBEN=1 B=A;EN=0 B=高阻態(tài)library ieee;use ieee.std_logic_1164.all;entity triout isport

19、(data_in:in std_logic; en:in std_logic; data_out:out std_logic);end triout;architecture behave of triout isbegin data_out=data_in when en=1 else Z; end behave; -注意此處的注意此處的“Z”要要大寫；大寫；library ieee;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_1164.all;entity triout isentity triout isport

20、port(data_in(data_in:in std_logic_vector(7 downto :in std_logic_vector(7 downto 0);0); en en:in std_logic;:in std_logic; data_out:out std_logic_vector(7 downto data_out:out std_logic_vector(7 downto 0);0);end triout;end triout;architecture behave of triout isbegin data_out Z); end behave; -注意此處的注意此處

21、的“Z”要要大寫；大寫；總結(jié)：VHDL+PLD組合邏輯電路設(shè)計邏輯問題邏輯問題邏輯輸入、輸出，邏輯函數(shù)邏輯輸入、輸出，邏輯函數(shù)n邏輯輸入邏輯輸入描述：描述：1 1位的輸入變量位的輸入變量標(biāo)準(zhǔn)邏輯類型，標(biāo)準(zhǔn)邏輯類型，std_logicstd_logic多位的輸入變量多位的輸入變量標(biāo)準(zhǔn)邏輯序列類型，標(biāo)準(zhǔn)邏輯序列類型，std_logic_vectorstd_logic_vectorn邏輯輸出邏輯輸出描述：描述：同邏輯輸入。同邏輯輸入。n邏輯關(guān)系邏輯關(guān)系描述：描述：列出真值表列出真值表 適用于輸入變量較少、或函數(shù)有效輸入值較少的情況。求取邏輯函數(shù)表達(dá)式求取邏輯函數(shù)表達(dá)式 輸出變量較少或輸出變量相互獨立

22、的情況。邏輯關(guān)系直接表述邏輯關(guān)系直接表述（邏輯關(guān)系概括直接邏輯描述） 碼制轉(zhuǎn)換等問題（數(shù)值運算類）例一：四位二進(jìn)制數(shù)轉(zhuǎn)換為BCD碼。entity bcd2bbcd2b isport(d:in std_logic_vector(3 downto 0); Bh,Bl:out std_logic_vector(3 downto 0);end bcd2bbcd2b;architecture aaaa of bcd2b issignal a,b:std_logic_vector(7 downto 0);begina = 0000&d;b = a when d10 else a+6;Bh = b(

23、7 downto 4);Bl = b(3 downto 0);end aa;architecture abab of bcd2b isbeginBh 9 else 0000;Bl 9 else d;end ab;例二：設(shè)計一位BCD碼加法器entity bcd_adder isport(d1,d2:in std_logic_vector(3 downto 0); Bh,Bl:out std_logic_vector(3 downto 0);end bcd_adder;architecture aaaa of bcd_adder issignal a,b,t,s:std_logic_vector

24、(7 downto 0);begina = 0000&d1;b = 0000&d2;t = a + b ;s = t when t10 else t+6;Bh = s(7 downto 4);Bl 1000-111D觸發(fā)器觸發(fā)器LIBRARYLIBRARY IEEE; IEEE;USEUSE IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL;ENTITYENTITY dff dff ISISPORTPORT( cp,d: IN STD_LOGIC;( cp,d: IN STD_LOGIC; q: OUT STD_LOGIC); q

25、: OUT STD_LOGIC);ENDEND dff; dff;ARCHITECTUREARCHITECTURE a a OFOF dff dff ISISBEGINBEGIN process process(cp)(cp) begin begin if if cpevent and cp=1 cpevent and cp=1 thenthen q=d; q=d; end if end if; ; end process end process; ;ENDEND a; a;(2)-A 簡單計數(shù)器設(shè)計計數(shù)器CLKQ3Q2Q1Q0四位加計數(shù)器四位加計數(shù)器LIBRARYLIBRARY ieee;

26、ieee;USEUSE ieee.std_logic_1164.ALL; ieee.std_logic_1164.ALL;USEUSE ieee.std_logic_unsigned.ALL; ieee.std_logic_unsigned.ALL;USEUSE ieee.std_logic_arith.ALL; ieee.std_logic_arith.ALL;ENTITYENTITY counter counter ISISPORTPORT( clk: in STD_LOGIC;( clk: in STD_LOGIC; q: q: bufferbuffer STD_LOGIC_vector

27、STD_LOGIC_vector(3 downto 0(3 downto 0););ENDEND counter; counter;ARCHITECTUREARCHITECTURE a a OFOF counter counter ISISBEGINBEGIN processprocess(clk) (clk) beginbegin ifif (clkevent and clk=1) (clkevent and clk=1) thenthen q=q+1; q=q+1; end ifend if; ; end processend process; ;ENDEND a; a;四位加計數(shù)器四位加

28、計數(shù)器計數(shù)器CLKCLR(2)-B 帶同步清零、同步置數(shù)功能的計數(shù)器LDQ3Q2Q1Q0 D3D2D1D0控制信號控制信號CLR、LD：具有更高優(yōu)先級：具有更高優(yōu)先級LIBRARYLIBRARY ieee; ieee;USEUSE ieee.std_logic_1164.ALL; ieee.std_logic_1164.ALL;USEUSE ieee.std_logic_unsigned.ALL; ieee.std_logic_unsigned.ALL;USEUSE ieee.std_logic_arith.ALL; ieee.std_logic_arith.ALL;ENTITYENTITY

29、counter counter ISISPORTPORT( clk,clr,ld: in STD_LOGIC;( clk,clr,ld: in STD_LOGIC; d: in STD_LOGIC_vector(3 downto d: in STD_LOGIC_vector(3 downto 0);0);q: q: bufferbuffer STD_LOGIC_vector(3 downto STD_LOGIC_vector(3 downto 0);0);ENDEND counter; counter;ARCHITECTUREARCHITECTURE a a OFOF counter coun

30、ter ISISBEGINBEGIN processprocess(clk) (clk) beginbegin ifif (clkevent and clk=1) (clkevent and clk=1) thenthen if if(clr=1)(clr=1) then then q=0000; q=0000; elsif elsif(ld=1)(ld=1)then then q=d; q=d; elseelse q=q+1; q=q+1; end ifend if; ; end if end if; ;end processend process; ;ENDEND a; a;計數(shù)器CLKC

31、LR(2)-C 帶異步清零、同步置數(shù)功能的計數(shù)器LDQ3Q2Q1Q0 D3D2D1D0LIBRARYLIBRARY ieee; ieee;USEUSE ieee.std_logic_1164.ALL; ieee.std_logic_1164.ALL;USEUSE ieee.std_logic_unsigned.ALL; ieee.std_logic_unsigned.ALL;USEUSE ieee.std_logic_arith.ALL; ieee.std_logic_arith.ALL;ENTITYENTITY counter counter ISISPORTPORT( clk,clr,ld

32、: in STD_LOGIC;( clk,clr,ld: in STD_LOGIC; d: in STD_LOGIC_vector(3 downto d: in STD_LOGIC_vector(3 downto 0);0);q: q: bufferbuffer STD_LOGIC_vector(3 downto STD_LOGIC_vector(3 downto 0);0);ENDEND counter; counter;ARCHITECTUREARCHITECTURE a a OFOF counter counter ISISBEGINBEGIN processprocess(clk,cl

33、r) (clk,clr) begin begin ifif(clr=1) (clr=1) thenthen q=“0000”; q=“0000”; elseelse if if (clkevent and clk=1) (clkevent and clk=1) thenthen if if(ld=1)(ld=1)then then q=d;q=d; elseelse q=q+1; q=q+1; end ifend if; ; end ifend if; ; end if end if; ; end processend process; ;ENDEND a; a;(2)-D 帶進(jìn)位計數(shù)器設(shè)計計

34、數(shù)器CLKQ3Q2Q1Q0四位加計數(shù)器四位加計數(shù)器COUTLIBRARYLIBRARY ieee; ieee;USEUSE ieee.std_logic_1164.ALL; ieee.std_logic_1164.ALL;USEUSE ieee.std_logic_unsigned.ALL; ieee.std_logic_unsigned.ALL;USEUSE ieee.std_logic_arith.ALL; ieee.std_logic_arith.ALL;ENTITYENTITY counter counter ISISPORTPORT( clk: in STD_LOGIC;( clk:

35、 in STD_LOGIC; q: q: bufferbuffer STD_LOGIC_vectorSTD_LOGIC_vector(3 downto (3 downto 0 0);); cout: out std_logic); cout: out std_logic); ENDEND counter; counter;ARCHITECTURE a OF counter ISBEGIN process(process(clkclk) ) variable variable tmp:std_logic_vector(3 tmp:std_logic_vector(3 downtodownto 0

36、);0); begin begin ifif (clkevent and clk=1) (clkevent and clk=1) thenthen q=q+1; q=q+1; tmp:=q+1; tmp:=q+1; ifif(tmp=15) (tmp=15) then then cout=1; cout=1; elseelse cout=0; cout=0; end ifend if; ; end ifend if; ;end process;end process;END a;END a;(3) 分頻器設(shè)計T Tclkclk = 1 us = 1 usT Tcoutcout = 10us =

37、 10us計數(shù)器就是對時鐘脈沖計數(shù)，同時計數(shù)器就是對時鐘脈沖計數(shù)，同時 計數(shù)器還是一個分頻器。計數(shù)器還是一個分頻器。（4）移位寄存器設(shè)計4位右移移位寄存器位右移移位寄存器Reset:異步清零異步清零右移移位寄存器右移移位寄存器dinresetclkQAQBQCQDlibrary ieee;use ieee.std_logic_1164.all;ENTITY shifter ISPORT( din : in std_logic; reset, clk : in std_logic; QA,QB,QC,QD : buffer std_logic); END shifter;ARCHITECTURE

38、 behave OF shifter ISBEGIN Process (reset,clk) Begin if(reset=1) then QA=0; QB=0; QC=0; QD=0; else if (clkEvent and clk = 1) then QA=din; QB=QA; QC=QB; QD=QC; end if; end if; end process; End behave;（5）狀態(tài)機(jī)設(shè)計l 我們可以用我們可以用輸入信號輸入信號X和和電路狀態(tài)電路狀態(tài)Q來描述來描述時序電路的邏輯功能，這時時序電路稱為時序電路的邏輯功能，這時時序電路稱為 狀態(tài)機(jī)狀態(tài)機(jī)（State Machi

39、ne）。）。l 根據(jù)輸出信號和輸入信號以及電路狀態(tài)的根據(jù)輸出信號和輸入信號以及電路狀態(tài)的關(guān)系，狀態(tài)機(jī)可以分為兩種：關(guān)系，狀態(tài)機(jī)可以分為兩種：穆爾（穆爾（Moore）型型和和米利（米利（Mealy）型）型。Y=FX,Q Y=FQ 米利（米利（Mealy）型：）型：穆爾（穆爾（Moore）型：）型：S0S20/01/0S31/0S11/10/00/10/01/0輸出信號和輸入信號無關(guān)。輸出信號和輸入信號無關(guān)。（1） More型狀態(tài)機(jī) 輸入信號影響狀態(tài)的轉(zhuǎn)換。輸入信號影響狀態(tài)的轉(zhuǎn)換。LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY more ISPORT

40、( Clk,reset: in Std_logic; din: in Std_logic; op: out Std_logic);END more;ARCHITECTURE a OF more ISTYPE STATE_TYPE IS (s0, s1, s2,s3);SIGNAL state: STATE_TYPE;BEGINPROCESSPROCESS (clk,reset) (clk,reset)BEGINBEGIN IfIf （reset = 1reset = 1） THENTHEN state = s0; state s0 = IFIF （din=1din=1） THENTHEN st

41、ate state = s1;= s1; elseelse state=s0;state s1 = IFIF （din=0din=0） THENTHEN state = s2;state = s2; elseelse state=s1; state s2 = IF IF （din=0din=0） THEN THEN state=s3;state=s3; else else state=s2; state s3 = IFIF （din=1din=1） THENTHEN state = s0;state = s0; elseelse state=s1;state=s1;END IFEND IF; ;End CaseEnd Case; ; End if; End if;End process; op=1 when （state=s1） else 0; END a;S0S20/01/0S31/1S11/10/00/00/01/1（2） Mealy型狀態(tài)機(jī) LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mealy ISPORT( Clk,reset: IN STD_L