芯片設(shè)計(jì)流程

1、Verilog基礎(chǔ)硬核實(shí)戰(zhàn)營培訓(xùn)關(guān)于Verilog及設(shè)計(jì)流程Veriog代碼結(jié)構(gòu) - 模塊、端口、注釋常數(shù)、運(yùn)算符芯片設(shè)計(jì)流程SpecificationBehavioral descriptionRTL descriptionFunctional verification & testGate level netlistLogic synthesisLogic verification and testingFloor planning, auto place & routePhysical layoutLayout verificationImplementation自上而下

2、的層次化結(jié)構(gòu)設(shè)計(jì)頂層模塊子模塊1子模塊2基本模塊3基本模塊2基本模塊1不同的設(shè)計(jì)方式 列出了一系列元件以及它們之間如何連接 純結(jié)構(gòu)化 就如原理圖，但是用文字來描述 Procedural code, 類似C編程 描述一個(gè)元件的功能以及如何實(shí)現(xiàn)該功能 很少的結(jié)構(gòu)化細(xì)節(jié) (除了模塊之間的互聯(lián)) Specifies transfer of data between registers Some structural information is available (RTL) Sometimes similar to behavior 模塊接口: 端口和參數(shù)聲明主體部分: 模塊的內(nèi)部部分附加部分 (可

3、選加)模塊的名字標(biāo)注：一行標(biāo)注 (/ .)一塊標(biāo)注 (/*.*/)模塊的描述(推薦的選項(xiàng))fin1in2inNout1out2outMmy_modulemodule my_module(out1, ., inN);output out1, ., outM;input in1, ., inN;. / declarations. / description of f (maybe. / sequential)endmodule對(duì)應(yīng)于電路中的一個(gè)元件可以跟其它元件連接，并被多次引用I/O端口在模塊的頂部列出，被聲明為Input、Output、或Inout（用于三態(tài)的總線中）端口聲明意味著變量都是Wi

4、res關(guān)鍵詞所有關(guān)鍵詞都是用小寫字母來定義例如 : module, endmoduleinput, output, inoutreg, integer, real, timenot, and, nand, or, nor, xorparameterbegin, endfork, joinspecify, hmodule Verilog設(shè)計(jì)中的基礎(chǔ)塊，用于構(gòu)建設(shè)計(jì)中的層次化 endmodule 結(jié)束一個(gè)模塊，不是一個(gè)語句 Module Declaration module module_name (module_port, module_port, );Example: module full_

5、adder (A, B, c_in,c_out, S);輸入定義：向量 input list of input identifiers;例如: input A, B, c_in;矢量 input范圍 list of input identifiers;例如: input15:0 A, B, data;輸出定義：向量舉例: output c_out, OV, MINUS;矢量舉例: output7:0 ACC, REG_IN, data_out; Nets: 硬件單元之間的物理連接 - 用關(guān)鍵詞 “wire”定義不保留他們的值，它們的數(shù)值來自一個(gè)門或其它模塊的驅(qū)動(dòng)不能通過一個(gè)initial 或

6、always 塊進(jìn)行賦值Registers: 類似計(jì)算機(jī)里的存儲(chǔ)器在通過一個(gè)initial或always塊賦值之前一直保留其數(shù)值可以用來模型化鎖存器、寄存器等，但不是完全對(duì)應(yīng)變量：wire/reg8h ax = 1010 xxxx12o 3zx7 = 011zzzxxx11112h046 - 12位長(zhǎng)的16進(jìn)制數(shù)Verilog的數(shù)值是沒有符號(hào)的：例如：C4:0 = A3:0 + B3:0;if A = 0110 (6) and B = 1010(-6)C = 10000 not 0000i.e., B is zero-padded, not sign-extendedVerilog的數(shù)字表示的

7、數(shù)字表示位數(shù)2進(jìn)制 b或B 8進(jìn)制 o 或 O10進(jìn)制 d or D16進(jìn)制 h or H連續(xù)的字符0-f, x, z 變量的多種形式Wires和registers可以是位、向量以及數(shù)組wire a; /一個(gè)簡(jiǎn)單的wiretri 15:0 dbus;/ 16-bit 三態(tài)總線try #(5,4,8) b;/ 帶延遲的Wirereg -1:4 vec;/ 6-bit的register（寄存器）triage (small) q;/ Wire stores a small chargeinteger imem0:1023;/ 1024整數(shù)的數(shù)組reg 31:0 dcache0:63;/ 一個(gè)32-b

8、it 的存儲(chǔ)器數(shù)據(jù)值四種數(shù)據(jù)的值數(shù)據(jù)表示類型：二進(jìn)制： 6b100101十六進(jìn)制： 6h250: 零, 邏輯低電平，錯(cuò)誤, 接地1: 一, 邏輯高電平, 電源X: 狀態(tài)未知Z: 高阻、三態(tài)、未連接,無驅(qū)動(dòng) 多位數(shù)的向量 A3:0 - 4 bits的向量: A3, A2, A1, A0 被當(dāng)成無符號(hào)的整數(shù)值 截?cái)郻its/vectors得到一個(gè)vector B7:0 = A3, A3, A3, A3, A3:0; B7:0 = 4A3, A3:0; 建議的寫法: a7:0 = b7:0 + c;不建議的寫法: a = b + c;端口定義寄存輸出時(shí)延聲明和事件控制傳輸延遲單個(gè)延時(shí): and #3

9、 G1 (y,a,b,c);上升/下降延時(shí) and #(3,5) G2 (y,a,b)Rise/Fall/Turnoff buff0 #(3,6.5) (y,x_in,en)Rise/Fall/Turnoff with Min:typ:Max buff1 #(3:4:5,4:5:6,7:8:9) (y,x_in,en);延時(shí)聲明- 以一個(gè)#符號(hào)標(biāo)明- Delays the execution of the statement immediately after- Inertial delay model (ignores glitches)- Additive with blocking st

10、atements事件控制聲明：- Edge sensitive, represented with a sign- Delays the execution until expression transitions Ex. always (clock) always (posedge clock) always (a or b)- Level sensitive, represented with wait statementEx. always wait (enable) #20 cnt = cnt + 1;Verilog中的運(yùn)算操作位操作邏輯運(yùn)算Reduction運(yùn)算算數(shù)運(yùn)算關(guān)系運(yùn)算移位運(yùn)

11、算位操作 - 操作符 & 位AND | 位OR 位NOT 位XOR or 位XNOR a = 4b1010; b = 4b1100;c = a;c = a & b;位操作 - 舉例c = a b;a = 4b1010;b = 2b11;邏輯運(yùn)算 & 邏輯與 AND | 邏輯或 OR ! 邏輯非 NOT Operands evaluated to ONE bit value: 0, 1 or x Result is ONE bit value: 0, 1 or xA = 1;A & B 1 & 0 0B = 0;A | !B 1 | 1 1C = x;C

12、| B x | 0 xbut C&B=0移位及條件執(zhí)行語句 右移 2;/ d = 0010, c = a 1;/ c = 0100 cond_expr ? true_expr : false_exprABYselY = (sel)? A : B;舉例 - 比較器module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) | (A & B); assign Alarger = (A & B);

13、assign Blarger = (A & B);endmodule / 通過4個(gè)1位的比較器構(gòu)建一個(gè)4位的比較器module Compare4(A4, B4, Equal, Alarger, Blarger); input 3:0 A4, B4; output Equal, Alarger, Blarger; wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3; Compare1 cp0(A40, B40, e0, Al0, Bl0); Compare1 cp1(A41, B41, e1, Al1, Bl1); Co

14、mpare1 cp2(A42, B42, e2, Al2, Bl2); Compare1 cp3(A43, B43, e3, Al3, Bl3); assign Equal = (e0 & e1 & e2 & e3); assign Alarger = (Al3 | (Al2 & e3) | (Al1 & e3 & e2) | (Al0 & e3 & e2 & e1); assign Blarger = (Alarger & Equal);endmoduleVerilog持續(xù)賦值assign A = X | (Y

15、& Z);assign B3:0 = 4b01XX;assign C15:0 = 16h00ff;assign #3 Cout, S3:0 = A3:0 + B3:0 + Cin;use of arithmetic operatormultiple assignment (concatenation)delay of performing computation, only used by simulator, not synthesisuse of Boolean operators( for bit-wise, ! for logical negation)bits can tak

16、e on four values(0, 1, X, Z)variables can be n-bits wide(MSB:LSB)always block always block Always waiting for a change to a trigger signal Then executes the bodymodule and_gate (out, in1, in2); input in1, in2; outputout; regout; always (in1 or in2) begin out = in1 & in2; endendmoduleNot a real r

17、egister!A Verilog registerNeeded because of assignment in always blockSpecifies when block is executed I.e., triggered by which signals Procedure that describes the function of a circuit Can contain many statements including if, for, while, case Statements in the always block are executed sequential

18、ly (Continuous assignments = are executed in parallel) Entire block is executed at once Final result describes the function of the circuit for current set of inputs intermediate assignments dont matter, only the final result begin/end used to group statements未完成觸發(fā)省去一個(gè)輸入觸發(fā)信號(hào)一般會(huì)導(dǎo)致一個(gè)時(shí)序電路例如: 這個(gè)”與”門的輸出取決

19、于輸入的歷史module and_gate (out, in1, in2); inputin1, in2; outputout; regout; always (in1) begin out = in1 & in2; endendmoduleIf/ Simple 4:1 muxmodule mux4 (sel, A, B, C, D, Y);input 1:0 sel;/ 2-bit control signalinput A, B, C, D;output Y;reg Y;/ target of assignment always (sel or A or B or C or D)

20、if (sel = 2b00) Y = A; else if (sel = 2b01) Y = B; else if (sel = 2b10) Y = C; else if (sel = 2b11) Y = D;endmodule/ Simple 4:1 muxmodule mux4 (sel, A, B, C, D, Y);input 1:0 sel;/ 2-bit control signalinput A, B, C, D;output Y;reg Y;/ target of assignment always (sel or A or B or C or D) if (sel0 = 0

21、) if (sel1 = 0) Y = A; else Y = B; else if (sel1 = 0) Y = C; else Y = D;endmodule另外一種方式Case - 1/ Simple 4-1 muxmodule mux4 (sel, A, B, C, D, Y);input 1:0 sel;/ 2-bit control signalinput A, B, C, D;output Y;reg Y;/ target of assignment always (sel or A or B or C or D) case (sel) 2b00: Y = A; 2b01: Y

22、= B; 2b10: Y = C; 2b11: Y = D; endcaseendmodule 順序執(zhí)行 只有第一個(gè)匹配的case被執(zhí)行(implicit break) 缺省的case可以用到 Conditions tested intop to bottom orderCase - 2/ Simple binary encoder (input is 1-hot)module encode (A, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assig

23、nment always (A) case (A) 8b00000001: Y = 0; 8b00000010: Y = 1; 8b00000100: Y = 2; 8b00001000: Y = 3; 8b00010000: Y = 4; 8b00100000: Y = 5; 8b01000000: Y = 6; 8b10000000: Y = 7; default: Y = 3bXXX;/ Dont care when input is not 1-hot endcaseendmodule/ Priority encodermodule encode (A, Y);input 7:0 A;

24、 / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assignment always (A) case (1b1) A0: Y = 0; A1: Y = 1; A2: Y = 2; A3: Y = 3; A4: Y = 4; A5: Y = 5; A6: Y = 6; A7: Y = 7; default: Y = 3bXXX;/ Dont care when input is all 0s endcaseendmoduleCase - 3/ simple encodermodule en

25、code (A, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assignment always (A) case (1b1)/ synthesis parallel-case A0: Y = 0; A1: Y = 1; A2: Y = 2; A3: Y = 3; A4: Y = 4; A5: Y = 5; A6: Y = 6; A7: Y = 7; default: Y = 3bX;/ Dont care when input is all 0s en

26、dcaseendmoduleLike case, but cases can include XX bits not used when evaluating the casesIn other words, you dont care about those bits!/ Priority encodermodule encode (A, valid, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputoutput valid;/ Asserted when an input is not all 0

27、sreg 2:0 Y;/ target of assignmentreg valid; always (A) begin valid = 1; casex (A) 8bXXXXXXX1: Y = 0; 8bXXXXXX10: Y = 1; 8bXXXXX100: Y = 2; 8bXXXX1000: Y = 3; 8bXXX10000: Y = 4; 8bXX100000: Y = 5; 8bX1000000: Y = 6; 8b10000000: Y = 7; default: begin valid = 0; Y = 3bX;/ Dont care when input is all 0s

28、 end endcase endendmoduleFor/repeat/forever/ simple encodermodule encode (A, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assignmentinteger i;/ Temporary variables for program onlyreg 7:0 test; always (A) begin test = 8b00000001; Y = 3bX; for (i = 0; i

29、 8; i = i + 1) begin if (A = test) Y = i; test = test 1; end endendmodule while (expression) statement Execute statement while expression is true repeat (expression) statement Execute statement a fixed number of times forever statement Execute statement forevermodule life (neighbors, self, out); inp

30、ut self; input 7:0 neighbors; output out; reg out; integer count; integer i; always (neighbors or self) begin count = 0; for (i = 0; i8; i = i+1) count = count + neighborsi; out = 0; out = out | (count = 3); out = out | (self = 1) & (count = 2); endendmodule另一個(gè)Behavioral的例子always block is execut

31、ed instantaneously, if there are no delays only the final result is usedintegers are temporary compiler variables Computing Conways Game of Life rule Cell with no neighbors or 4 neighbors dies; with 2-3 neighbors lives測(cè)試設(shè)計(jì)的電路(CUD)84產(chǎn)生輸出到設(shè)計(jì)的電路中檢查設(shè)計(jì)電路的輸出Test benchStimulus blockTestbench系統(tǒng)模型系統(tǒng)模型激勵(lì)響應(yīng)結(jié)果檢

32、查測(cè)試臺(tái)(test bench)module main;reg a, b, c; wire sum, carry;fulladder add(a,b,c,sum,carry);initialbegin a = 0; b = 0; c = 0; #5 a = 0; b = 1; c = 0; #5 a = 1; b = 0; c = 1; #5 a = 1; b = 1; c = 1; #5endendmodule測(cè)試模塊的結(jié)構(gòu) module ;數(shù)據(jù)類型聲明調(diào)用被測(cè)試的模塊施加激勵(lì)顯示結(jié)果endmodulemodule stimulus;reg clk;reg reset;wire3:0 q;/

33、 instantiate the design blockripple_carry_counter r1(q, clk, reset);/ Control the clockinitial clk = 1b0;always #5 clk = clk;/ Control the resetinitialbeginreset = 1b1;#15 reset = 1b0;#180 reset = 1b1;#10 reset = 1b0;#20 $stop;end/ Monitor the outputs initial $monitor($time, Output q = %d, q);endmod

34、ule測(cè)試臺(tái)產(chǎn)生輸入激勵(lì)信號(hào)，也經(jīng)常包括對(duì)數(shù)據(jù)的觀察仿真仿真行為Scheduled using an event queueNon-preemptive, no prioritiesA process must explicitly request a context switchEvents at a particular time unorderedScheduler runs each event at the current time, possibly scheduling more as a resultEvaluation events compute functions of

35、inputsUpdate events change outputsSplit necessary for delays, nonblocking assignments, etc.Evaluation event reads values of b and c, adds them, and schedules an update eventa = b + cUpdate event writes new value of a and schedules any evaluation events that are sensitive to a change on a兩種類型的事件Concu

36、rrent processes (initial, always) run until they stop at one of the followin#42Schedule process to resume 42 time units from nowwait(cf & of)Resume when expression “cf & of” becomes true(a or b or y)Resume when a, b, or y changes(posedge clk)Resume when clk changes from 0 to 1仿真Infinite loop

37、s are possible and the simulator does not check for themThis runs forever: no context switch allowed, so ready can never changewhile (ready) count = count + 1;Instead, usewait(ready);Race conditions abound in VerilogThese can execute in either order: final value of a undefined:always (posedge clk) a

38、 = 0;always (posedge clk) a = 1;Semantics of the language closely tied to simulator implementationContext switching behavior convenient for simulation, not always best way to modelUndefined execution order convenient for implementing event queueVerilog基本單元 只是基本的邏輯門 and or not buf xor nand nor xnor b

39、ufif1, bufif0 notif1, notif0所有邏輯門的Verilog編碼 module gates(a, b, y1, y2, y3, y4, y5, y6, y7); input 3:0 a, b; output 3:0 y1, y2, y3, y4, y5, y6, y7;/* 7種不同的邏輯門工作于4位的總線上 */assign y1= a; / NOT gateassign y2= a & b; / AND gateassign y3= a | b; / OR gateassign y4= (a & b); / NAND gateassign y5= (a

40、 | b); / NOR gateassign y6= a b; / XOR gateassign y7= (a b); / XNOR gateendmodule示例 - 加法器module half_adder(S, C, A, B);output S, C;input A, B;wire S, C, A, B;assign S = A B;assign C = A & B;endmoduleHalfAdderABSCABSCHalfAdder ha2ABSCHalfAdder 1ha1ABSCtin1in2cincoutsumI1I2I3module full_adder(sum,

41、 cout, in1, in2, cin);output sum, cout;input in1, in2, cin;wire sum, cout, in1, in2, cin;wire I1, I2, I3;half_adder ha1(I1, I2, in1, in2);half_adder ha2(sum, I3, I1, cin);assign cout = I2 | I3;endmoduleInstancenameModulename舉例: 全加器module full_adder(sum, cout, in1, in2, cin);output sum, cout;input in

42、1, in2, cin;wire sum, cout, in1, in2, cin;wire I1, I2, I3;half_adder ha1(I1, I2, in1, in2);half_adder ha2(sum, I3, I1, cin);assign cout = I2 | I3;endmoduleInstancenameModulenameHalfAdder ha2ABSCHalfAdder 1ha1ABSCin1in2cincoutsumI1I2I3賦值 Continuous assignments assign values to nets (vector and scalar

43、) They are triggered whenever simulation causes the value of the right-hand side to change Keyword “assign”e.g. assign out = in1 & in2; Procedural assignments drive values onto registers (vector and scalar) They Occur within procedures such as always and initial They are triggered when the flow

44、of execution reaches them (like in C) Blocking and Non-Blocking procedural assignments Procedural Assignments Blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement Nonblocking assignm

45、ent statement (= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit基于延時(shí)的定時(shí)控制 Delay Control (#) Expression specifies the time duration between initially encountering the statement and when the statement actually executes.

46、 Delay in Procedural Assignments Inter-Statement Delay Intra-Statement Delay For example: Inter-Statement Delay #10 A = A + 1; Intra-Statement DelayA = #10 A + 1; 時(shí)序表述： if/casemodule decoder(o,enb_,sel) ;output 7:0 o ;input enb_ ;input 2:0 sel ;reg 7:0 o ;always (enb_ or sel) if(enb_)o = 8b1111_1111

47、 ; elsecase(sel)3b000 : o = 8b1111_1110 ;3b001 : o = 8b1111_1101 ;3b010 : o = 8b1111_1011 ;3b011 : o = 8b1111_0111 ;3b100 : o = 8b1110_1111 ;3b101 : o = 8b1101_1111 ;3b110 : o = 8b1011_1111 ;3b111 : o = 8b0111_1111 ;default : o = 8bx ;endcase endmoduleif (expr1)true_stmt1;else if (expr2)true_stmt2;.

48、elsedef_stmt;E.g. 4-to-1 mux:module mux4_1(out, in, sel);output out;input 3:0 in;input 1:0 sel;reg out;wire 3:0 in;wire 1:0 sel;always (in or sel)if (sel = 0)out = in0;else if (sel = 1)out = in1;else if (sel = 2)out = in2;else out = in3;endmodulecase (expr)item_1, ., item_n: stmt1;item_n+1, ., item_

49、m: stmt2;.default:def_stmt;endcaseE.g. 4-to-1 mux:module mux4_1(out, in, sel);output out;input 3:0 in;input 1:0 sel;reg out;wire 3:0 in;wire 1:0 sel;always (in or sel)case (sel)0: out = in0;1: out = in1;2: out = in2;3: out = in3;endcaseendmodule帶使能控制的3-to 8譯碼矢量Nets and Registers can be declared as v

50、ectorsIf no bitwidth is specified, 1 bit is assumedwire 7:0 a;reg 0:31 addr1, addr2;Subsets of bits can be selectedaddr12:0 = addr23:1;其它數(shù)據(jù)類型Verilog allows integers, real, and time typesArrays can be made from other types- Arrays can be multidimensional- A vector is conceptually a single elements wi

51、th many bits- An array is many elements put togetherwire 7:0 x; / a vectorwire x 7:0; / an arraywire 7:0 x 7:0; / an array of vectorswire x7:07:0; / a two dimensional arrayParameters are constantsparameter line_width=80;Dataflow Descriptions, Continuous Assignmentsassign out = i1 & i2;Use the as

52、sign keyword (in most cases)Left hand side must be a net of some kind (scalar or vector), not a registerRight hand side can be registers, nets, or function callsContinuous assignments are always active. Execution hard to traceThey are evaluated whenever a right hand side operand changes valueDelays

53、(inertial) can be added to represent component delaysassign #10 out = i1 & i2;Continuous assignment can be implicit in a net declarationwire out = i1 & i2;module edge_dff(q, qbar, d, clk, clear);/ Inputs and outputsoutput q,qbar;input d, clk, clear;/ Internal variableswire s, sbar, r, rbar,c

54、bar;/Make complement of clearassign cbar = clear;/ Input latchesassign sbar = (rbar & s),s = (sbar & cbar & clk),r = (rbar & clk & s),rbar = (r & cbar & d);/ Output latchassign q = (s & qbar),qbar = (q & r & cbar);endmoduleBehavioral Modeling, Structured Proce

55、duresInitial blocks- The block executes only once- By default, starts at time 0 (but this can be changed)- Often used for initializationAlways blocks and initial blocks- Parallel constructs: all blocks can execute in parallelmodule stimulus;reg x,y, a,b, m;initialbegin#5 a = 1b1; #25 b = 1b0;endinit

56、ialbegin#10 x = 1b0;#25 y = 1b1;endendmoduleAlways blocks- The block executes in an infinite loop- By default, starts at time 0 (but this can be changed)- Represents a concurrent hardware block- Needs a delaymodule clock_gen; reg clock;initial clock = 1b0;always #10 clock = clock;initial #1000 $fini

57、sh;endmoduleinitial begin imperative statements endRuns when simulation startsTerminates when control reaches the endGood for providing stimulusalways begin imperative statements endRuns when simulation startsRestarts when control reaches the endGood for modeling/specifying hardwareRun until they en

58、counter a delayinitial begin #10 a = 1; b = 0; #10 a = 0; b = 1;endor a wait for an eventalways (posedge clk) q = d;always begin wait(i); a = 0; wait(i); a = 1; endInitial and AlwaysProcedural StatementsVerilog has two types of procedural assignmentFundamental problem:In a synchronous system, all fl

59、ip-flops sample simultaneouslyIn Verilog, always (posedge clk) blocks run in some undefined sequenceBlocking Assignments- Represented with a = sign- All blocking assignments are executed in sequencemodule dummy;reg x, y, z;reg 15:0 reg_a, reg_b;integer count;initialbegin x = 0; y = 1; z = 1; count =

60、 0; reg_a = 16b0; reg_b = reg_a; reg_a2 = #15 1; reg_b15:13 = #10 x, y, z; count = count + 1;endNon-Blocking Assignments- Represented with a = sign- All non-blocking assignments are executed in parallel- Try not to mix with blocking assignmentsmodule dummy;reg x, y, z;reg 15:0 reg_a, reg_b;integer count;initialbegin x = 0; y = 1; z = 1; count = 0; reg_a = 16b0; reg_b = reg_a; reg_a2 = #15 1; reg_b15:13 = #10 x, y, z; count = count + 1;end時(shí)序電路設(shè)計(jì) a feedback path t