數(shù)字鐘VHDL程序

1、精選文檔大連理工大學(xué)本科實(shí)驗(yàn)報(bào)告題目:數(shù)字鐘的VHDL設(shè)計(jì)課程名稱： 數(shù)字電路課程設(shè)計(jì) 學(xué)院（系）： 電子信息與電氣工程學(xué)部 專 業(yè)： 電子信息工程 班 級(jí)： 學(xué)生姓名： 學(xué) 號(hào)： 完成日期： 成 績(jī)： 2013 年 12 月 15 日數(shù)字鐘的VHDL設(shè)計(jì)1. 設(shè)計(jì)任務(wù)及要求：設(shè)計(jì)任務(wù)：設(shè)計(jì)一臺(tái)能顯示時(shí)、分、秒的數(shù)字鐘。具體要求如下：（1）設(shè)計(jì)一個(gè)數(shù)字鐘，能夠顯示當(dāng)前時(shí)間，分別用6個(gè)數(shù)碼管顯示小時(shí)、分鐘、秒鐘的時(shí)間，秒針的計(jì)數(shù)頻率為1Hz，可由系統(tǒng)脈沖分頻得到。（2）在整點(diǎn)進(jìn)行提示，可通過(guò)LED閃爍實(shí)現(xiàn)，閃爍頻率及花型可自己設(shè)計(jì)。（3）能夠調(diào)整小時(shí)和分鐘的時(shí)間，調(diào)整的形式為通過(guò)按鍵進(jìn)行累加。（

2、4）具有鬧鐘功能，鬧鐘時(shí)間可以任意設(shè)定（設(shè)定的形式同樣為通過(guò)按鍵累加），并且在設(shè)定的時(shí)間能夠進(jìn)行提示，提示同樣可以由LED閃爍實(shí)現(xiàn)設(shè)計(jì)要求：（1） 編寫(xiě)設(shè)計(jì)報(bào)告，要求包括方案選擇、程序代碼清單、調(diào)試過(guò)程、測(cè)試結(jié)果及心得體會(huì)。2. 設(shè)計(jì)原理時(shí)顯示器秒顯示器分顯示器時(shí)譯碼器秒譯碼器分譯碼器報(bào)時(shí)時(shí)計(jì)數(shù)器分計(jì)數(shù)器秒計(jì)數(shù)器校時(shí)電路 1HZ分頻器振蕩器圖1 數(shù)字鐘的系統(tǒng)框圖該系統(tǒng)由振蕩器、分頻器、“時(shí)、分、秒”計(jì)數(shù)器、譯碼器及顯示器、校時(shí)電路、整點(diǎn)報(bào)時(shí)電路等組成。石英晶體振蕩器和分頻器產(chǎn)生整個(gè)系統(tǒng)的時(shí)基信號(hào)，它直接決定計(jì)時(shí)系統(tǒng)的精度。“秒計(jì)數(shù)器”采用六十進(jìn)制計(jì)數(shù)器，每累計(jì)60秒向“分計(jì)數(shù)器”進(jìn)位；“分計(jì)數(shù)

3、器”采用六十進(jìn)制計(jì)數(shù)器，每累計(jì)60分向“時(shí)計(jì)數(shù)器”進(jìn)位；“時(shí)計(jì)數(shù)器”采用二十四進(jìn)制計(jì)數(shù)器，按照“24翻1”規(guī)律計(jì)數(shù)?！皶r(shí)、分、秒”計(jì)數(shù)器的輸出經(jīng)譯碼器送顯示器顯示。校時(shí)電路用來(lái)當(dāng)計(jì)時(shí)出現(xiàn)誤差時(shí)對(duì)“時(shí)、分、秒”進(jìn)行校對(duì)調(diào)整。整點(diǎn)報(bào)時(shí)電路是根據(jù)計(jì)時(shí)系統(tǒng)的輸出狀態(tài)產(chǎn)生一脈沖信號(hào)，然后去觸發(fā)音頻發(fā)生器實(shí)現(xiàn)報(bào)時(shí)。 3. 設(shè)計(jì)過(guò)程3.1. 設(shè)計(jì)思路時(shí)鐘脈沖信號(hào)作為數(shù)字鐘的時(shí)間基準(zhǔn)，再經(jīng)分頻器輸出標(biāo)準(zhǔn)秒脈沖。秒計(jì)數(shù)器計(jì)滿60后向分計(jì)數(shù)器進(jìn)位，分計(jì)數(shù)器計(jì)滿60后向小時(shí)計(jì)數(shù)器進(jìn)位，小時(shí)計(jì)數(shù)器是計(jì)滿24后，系統(tǒng)自動(dòng)復(fù)位重新開(kāi)始計(jì)數(shù)。計(jì)數(shù)器的輸出經(jīng)譯碼電路后送到顯示器顯示。可以用校時(shí)電路進(jìn)行校時(shí)。整點(diǎn)報(bào)時(shí)電路在每小

4、時(shí)的最后50秒開(kāi)始報(bào)時(shí)間隔一秒報(bào)一次時(shí)直至下一小時(shí)開(kāi)始。3.2. 數(shù)字鐘的設(shè)計(jì)方案數(shù)字鐘的設(shè)計(jì)包括編碼模塊、分頻模塊、秒計(jì)時(shí)模塊、分計(jì)時(shí)模塊、小時(shí)計(jì)時(shí)模塊、鬧鐘模塊和報(bào)時(shí)模塊。該數(shù)字鐘可以實(shí)現(xiàn)3個(gè)功能：計(jì)時(shí)功能、報(bào)時(shí)功能、鬧鈴和設(shè)置時(shí)間功能。3.2.1. 編碼模塊編碼模塊主要是對(duì)時(shí)、分、秒的設(shè)置輸入。3.2.2. 分頻模塊在數(shù)字鐘的設(shè)計(jì)中，外部輸入時(shí)鐘信號(hào)clk1的頻率為50Mhz，其分頻后的頻率為clk，使其分頻結(jié)果為1hz，用來(lái)提供給秒計(jì)時(shí)模塊、分計(jì)時(shí)模塊、小時(shí)計(jì)時(shí)模塊。3.2.3. 秒計(jì)時(shí)模塊將“秒計(jì)時(shí)脈沖”clk接信號(hào)源單元的1HZ脈沖信號(hào)，此時(shí)秒顯示將從00計(jì)時(shí)到59，然后回到00，

5、重新計(jì)時(shí)。在秒位進(jìn)行計(jì)時(shí)的過(guò)程中。秒計(jì)時(shí)器是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有置數(shù)和計(jì)數(shù)功能。其中reset為置數(shù)信號(hào)，當(dāng)reset為1時(shí)，秒計(jì)時(shí)器置數(shù)。clk為驅(qū)動(dòng)秒計(jì)時(shí)器的時(shí)鐘，sec2、sec1為秒計(jì)時(shí)器的高位和低位輸出。3.2.4. 分計(jì)時(shí)模塊分計(jì)時(shí)電路：將“分計(jì)時(shí)脈沖”clk接信號(hào)源單元的c1脈沖信號(hào)，此時(shí)分顯示將從00計(jì)時(shí)到59，然后回到00，重新計(jì)時(shí)。在分位進(jìn)行計(jì)時(shí)的過(guò)程中。分計(jì)時(shí)器是由一個(gè)60進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有置數(shù)和計(jì)數(shù)功能。其中rese為置數(shù)信號(hào)，當(dāng)reset為1時(shí)，分計(jì)時(shí)器置數(shù)。fen4、fen3為分計(jì)時(shí)器的高位和低位輸出。3.2.5. 小時(shí)計(jì)時(shí)模塊將“小時(shí)計(jì)時(shí)脈沖”

6、clk接信號(hào)源單元的c2脈沖信號(hào)，此時(shí)小時(shí)顯示將從00計(jì)時(shí)到23，然后回到00，重新計(jì)時(shí)。時(shí)計(jì)時(shí)器是由一個(gè)24進(jìn)制的計(jì)數(shù)器構(gòu)成的，具有置數(shù)和計(jì)數(shù)功能。其中的reset為置數(shù)信號(hào)，當(dāng)reset為1時(shí)，時(shí)計(jì)時(shí)器置數(shù)。shi6、shi5為時(shí)計(jì)時(shí)器的高位和低位輸出。3.2.6. 報(bào)時(shí)模塊當(dāng)分位到59時(shí)，秒位計(jì)到51秒、53秒、55秒、57秒、59秒時(shí)報(bào)時(shí)一次，而后小時(shí)位加1。3.2.7.VHDL 引腳分配圖4. 源程序4.1. 數(shù)字鐘整體程序整個(gè)程序分為六個(gè)部分，分別為分頻部分、校時(shí)部分、秒部分、分部分、小時(shí)部分和報(bào)時(shí)部分。4.2. VHDL程序及波形分析4.2.1. VHDL程序library ie

7、ee;-count60use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count60 isport(clk:in std_logic; reset:in std_logic; set:in std_logic; inc:in std_logic; out1:out std_logic_vector(3 downto 0); out2:out std_logic_vector(3 downto 0); c:out std_logic; alight:out std_logic); end;architectur

8、e run2 of count60 issignal ts1,ts2,as1,as2:std_logic_vector( 3 downto 0):="0000"signal tclk,aclk: std_logic;beginprocess(inc,clk,set)-根據(jù)設(shè)置模式，處理inc上的脈沖信號(hào)beginif set='0' then -時(shí)間調(diào)整模式aclk<='0'if clk='1' and inc='1' then -clk=1則tclk<=0，通過(guò)挖洞方式添加一個(gè)脈沖tclk<

9、='0'elsif clk='0' and inc='1' then -clk=0,則tclk<=1,產(chǎn)生一個(gè)高電平，添加一脈沖tclk<='1'elsetclk<=clk;end if;elsif set='1' then -鬧鈴調(diào)整模式tclk<=clk;aclk<=inc; -inc上的脈沖直接修改鬧鈴定時(shí)值end if;end process;process(tclk,reset) beginif(reset='0')then ts1<="000

10、0"ts2<="0000" elsif(tclk'event and tclk='1')then if ts1="1001" then ts1<="0000" if ts2="0101" then ts2<="0000" else ts2<=ts2+1; end if; else ts1<=ts1+1;-計(jì)數(shù)過(guò)程 end if;end if;end process;-結(jié)束進(jìn)程process(aclk,reset) beginif(r

11、eset='0')then as1<="0000"as2<="0000" elsif(aclk'event and aclk='1')then if as1="1001" then as1<="0000" if as2="0101" then as2<="0000" else as2<=as2+1; end if; else as1<=as1+1;-計(jì)數(shù)過(guò)程 end if;end if;end pro

12、cess;-結(jié)束進(jìn)程process(ts1,ts2,as1,as2)- 顯示時(shí)間或鬧鈴定時(shí)值begin if set='0' then - 顯示時(shí)間out1<=ts1;out2<=ts2;else - 顯示定時(shí)值out1<=as1;out2<=as2;end if;end process;process(ts1,ts2,as1,as2) -判斷定時(shí)值與時(shí)間值相等，輸出鬧鈴觸發(fā)信號(hào)begin if (ts1="1001" and ts2="0101") then c<='1' else c<

13、;='0' end if;if ts1=as1 and ts2=as2 thenalight<='1'elsealight<='0'end if;end process;end run2;library ieee;-count24use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count24 isport(clk:in std_logic; reset:in std_logic; set:in std_logic; inc:in std_logic;

14、 out1:out std_logic_vector(3 downto 0); out2:out std_logic_vector(3 downto 0); c:out std_logic;alight:out std_logic); end; architecture run1 of count24 issignal ts1,ts2,as1,as2:std_logic_vector( 3 downto 0):="0000"signal tclk,aclk: std_logic;beginprocess(inc,clk,set)-根據(jù)設(shè)置模式，處理inc上的脈沖信號(hào)begi

15、nif set='0' then -時(shí)間調(diào)整模式aclk<='0'if clk='1' and inc='1' then -clk=1則tclk<=0，通過(guò)挖洞方式添加一個(gè)脈沖tclk<='0'elsif clk='0' and inc='1' then -clk=0,則tclk<=1,產(chǎn)生一個(gè)高電平，添加一脈沖tclk<='1'elsetclk<=clk;end if;elsif set='1' then -鬧鈴調(diào)

16、整模式tclk<=clk;aclk<=inc; -inc上的脈沖直接修改鬧鈴定時(shí)值end if;end process;process(tclk,reset) beginif(reset='0')then ts1<="0000"ts2<="0000" elsif(tclk'event and tclk='1')then if ts2<"0010" then if(ts1="1001") then ts1<="0000"t

17、s2<=ts2+1; else ts1<=ts1+1; end if; elsif(ts2="0010") then if(ts1="0011") then ts1<="0000"ts2<="0000" -計(jì)數(shù)過(guò)程 else ts1<=ts1+1; end if; end if;end if;end process;-結(jié)束進(jìn)程process(aclk,reset) beginif(reset='0')then as1<="0000"as2<

18、;="0000" elsif(aclk'event and aclk='1')then if as2<"0010" then if(as1="1001") then as1<="0000"as2<=as2+1; else as1<=as1+1; end if; elsif(as2="0010") then if(as1="0011") then as1<="0000"as2<="0000

19、" -計(jì)數(shù)過(guò)程 else as1<=as1+1; end if; end if;end if;end process;-結(jié)束進(jìn)程process(ts1,ts2,as1,as2)- 顯示時(shí)間或鬧鈴定時(shí)值begin if set='0' then - 顯示時(shí)間out1<=ts1;out2<=ts2;else - 顯示定時(shí)值out1<=as1;out2<=as2;end if;end process;process(ts1,ts2,as1,as2) -判斷定時(shí)值與時(shí)間值相等，輸出鬧鈴觸發(fā)信號(hào)begin if ts1="0010&quo

20、t; and ts2="0011" then c<='1' else c<='0' end if;if ts1=as1 and ts2=as2 thenalight<='1'elsealight<='0'end if;end process;end run1;library ieee;-xianshiuse ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport(clk:in std_lo

21、gic_vector(3 downto 0); qq:out std_logic_vector(6 downto 0);end;architecture run3 of xianshi isbeginprocess(clk)begincase clk iswhen "0000"=>qq<="1000000"when "0001"=>qq<="1111001"when "0010"=>qq<="0100100"when "0011&

22、quot;=>qq<="0110000"when "0100"=>qq<="0011001"when "0101"=>qq<="0010010"when "0110"=>qq<="0000010"when "0111"=>qq<="1111000"when "1000"=>qq<="0000000"when

23、 others=>qq<="0010000"end case;end process;end;library ieee;-shizhonguse ieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entity shizhong isport (clk:in std_logic;-PIN_N2 reset:in std_logic;-PIN_N25 set:in std_logic;-PIN_N26 inc1,inc2,inc3:in std_logic;-PIN_G26,PIN_N23,PIN_P23

24、shi6,shi5,fen4,fen3,miao2,miao1:out std_logic_vector(6 downto 0); alight,light1,light2:out std_logic);-鬧鈴end;architecture run of shizhong issignal sshi6,sshi5,sfen4,sfen3,smiao2,smiao1: std_logic_vector(3 downto 0);signal c1,c2,c3,clk1s,clk2ms,clk1ms:std_logic;signal alight1,alight2,alight3:std_logi

25、c;component count60port(clk:in std_logic; reset:in std_logic; set:in std_logic; inc:in std_logic; out1:out std_logic_vector(3 downto 0); out2:out std_logic_vector(3 downto 0); c:out std_logic; alight:out std_logic);end component;component count24port(clk:in std_logic; reset:in std_logic; set:in std_

26、logic; inc:in std_logic; out1:out std_logic_vector(3 downto 0); out2:out std_logic_vector(3 downto 0); c:out std_logic;alight:out std_logic);end component;component xianshi port(clk:in std_logic_vector(3 downto 0); qq:out std_logic_vector(6 downto 0);end component;beginprocess(clk)variable count1:in

27、teger range 0 to 49999999;begin if(clk'event and clk='1')then count1:=count1+1;-在clk 的上升沿計(jì)數(shù) if count1<=24999999 then clk1s<='0' elsif count1<=49999999 then clk1s<='1' else count1:=0; end if; end if; end process;-產(chǎn)生周期為1s的時(shí)鐘信號(hào)process(clk)variable count2:integer

28、range 0 to 99999;begin if(clk'event and clk='1')then count2:=count2+1;-在clk 的上升沿計(jì)數(shù) if count2<=49999 then clk2ms<='0' elsif count2<=99999 then clk2ms<='1' else count2:=0; end if;end if;end process; -產(chǎn)生周期為2ms的時(shí)鐘信號(hào) 500Hzprocess(clk)variable count3:integer range 0

29、 to 49999;begin if(clk'event and clk='1')then count3:=count3+1;-在clk 的上升沿計(jì)數(shù) if count3<=24999 then clk1ms<='0' elsif count3<=49999 then clk1ms<='1' else count3:=0; end if;end if;end process;-產(chǎn)生周期為1ms的時(shí)鐘信號(hào)1000Hzprocess(alight1,alight2,alight3)beginif alight1='1' and alight2='1' and alight3='1'then alight<='1' else alight<='0'end if;end process;process(sfen4,sfen3,smiao2,smiao1)beginif sfen4="0101" and sfen3="1001" thenif smiao2="0101" thenif smiao1="