基于VHDL的八路彩燈控制器

1、沈陽理工大學(xué)課程設(shè)計(jì)專用紙NO.15目錄1.任務(wù)需求22. 總體設(shè)計(jì)22.1 各個(gè)花樣的狀態(tài)圖22.2總體框圖43. 模塊設(shè)計(jì)43.1分頻器模塊43.2花樣一模塊53.3花樣二模塊63.4花樣三模塊83.5頂層設(shè)計(jì)104. 仿真圖114.1分頻器仿真波形114.2花樣一仿真波形114.3花樣二仿真波形124.4花樣三仿真波形134.5總體仿真波形135.心得體會(huì)146.參考文獻(xiàn)151.任務(wù)需求現(xiàn)今生活中，市場(chǎng)上未能吸取顧客的注意，高出各式各樣的方法，其中彩燈的裝飾便是其中非常普遍的一種。使用彩燈即可起裝飾宣傳作用，又可以現(xiàn)場(chǎng)氣氛，城市也因?yàn)楸姸嗟牟薀舳兊脿N爛輝煌。VHDL語言作為可編程邏輯器

2、件的標(biāo)準(zhǔn)語言描述能力強(qiáng)，覆蓋面廣，抽象能力強(qiáng)，在實(shí)際應(yīng)用中越來越廣泛。在這個(gè)階段，人們開始追求貫徹整個(gè)系統(tǒng)設(shè)計(jì)的自動(dòng)化，可以從繁重的設(shè)計(jì)工作中徹底解脫出來，把精力集中在創(chuàng)造性的方案與概念構(gòu)思上，從而可以提高設(shè)計(jì)效率，縮短產(chǎn)品的研制周期。整個(gè)過程通過EDA工具自動(dòng)完成，大大減輕了設(shè)計(jì)人員的工作強(qiáng)度，提高了設(shè)計(jì)質(zhì)量，減少了出錯(cuò)的機(jī)會(huì)。要求設(shè)計(jì)一個(gè)8路彩燈控制器,要求彩燈可以演示以下花型：（1） 從兩邊向中間亮，再從中間向兩邊亮；（2） 實(shí)現(xiàn)淡入淡出效果（3） 從左至右逐個(gè)亮，在從右到左逐個(gè)亮；2. 總體設(shè)計(jì)2.1 各個(gè)花樣的狀態(tài)圖當(dāng)選擇花樣一時(shí)狀態(tài)圖如下：S0=”ZZZZZZZZ” S1=1000

3、0001S2=01000010S3=00100100 S4=00011000 S5=00100100S6=01000010S0S1CLRS2S6S3S5S4當(dāng)選擇花樣二時(shí)狀態(tài)圖如下： S0=”ZZZZZZZZ” S1=00000000S2=10000000S3=11000000S4=11100000 S5=11110000S6=11111000S7=”11111100”S8=”11111110” S9=11111111S10=01111111S11=00111111S12=00011111 S13=00001111S14=00000111S15=”00000011”S16=”00000001”

4、S0s1 CLRS16S2 S4S15S5s14s6s13S7s12S8s11S9s10 當(dāng)選擇花樣三時(shí)狀態(tài)圖如下：S0=”ZZZZZZZZ” S1=10000000S2=01000000S3=00100000S4=00010000 S5=00001000S6=00000100S7=”00000010”S8=”00000001” S9=00000010S10=00000100S11=00001000S12=0001000 S13=00100000S14=01000000S0s1 CLRS2s14 S3s13S4s12s11S5s10s6S7S9S82.2總體框圖分頻器 CLK狀態(tài)機(jī)LED顯示選

5、擇器 XUAN 3. 模塊設(shè)計(jì)3.1分頻器模塊 -由于機(jī)器時(shí)鐘周期太短,不能滿足要求 -此模塊實(shí)現(xiàn)分頻,得到需要的時(shí)鐘LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;USE IEEE.std_logic_unsigned.ALL;ENTITY fenpinqi ISPORT( CLK:IN STD_LOGIC; -原機(jī)器時(shí)鐘 CLR:IN STD_LOGIC; CLK1:OUT STD_LOGIC); -分頻后的時(shí)鐘END fenpinqi;ARCHITECTURE ART OF fenpinqi ISSIGNAL CK:STD_LOGIC; BEGIN P

6、ROCESS(CLK,CLR)IS VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN IF CLR=1 THEN CK=0; TEMP:=000; ELSIF(CLKEVENT AND CLK=1)THEN IF TEMP=111 THEN TEMP:=000; CK=NOT CK; ELSE TEMP:=TEMP+1; END IF; END IF; END PROCESS; CLK1=CK;END ART;3.2花樣一模塊 -用分頻器分頻后的時(shí)鐘來顯示花樣實(shí)現(xiàn) -從兩邊向中間亮，再從中間向兩邊亮；LIBRARY IEEE;USE IEEE.

7、STD_LOGIC_1164.ALL;ENTITY hy1 IS PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY hy1;ARCHITECTURE ART OF hy1 IS TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6); -設(shè)計(jì)狀態(tài)機(jī),實(shí)現(xiàn)花樣轉(zhuǎn)換 SIGNAL CURRENT_STATE:STATE; SIGNAL LIGHT:STD_LOGIC_VECTO

8、R(7 DOWNTO 0); BEGIN PROCESS(CLR,CLK1,XUAN)IS -定義花樣(1為燈亮,0為燈滅) CONSTANT L1:STD_LOGIC_VECTOR(7 DOWNTO 0):=10000001; CONSTANT L2:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000010; CONSTANT L3:STD_LOGIC_VECTOR(7 DOWNTO 0):=00100100; CONSTANT L4:STD_LOGIC_VECTOR(7 DOWNTO 0):=00011000; CONSTANT L5:STD_LOGIC_VECTOR(

9、7 DOWNTO 0):=00100100;CONSTANT L6:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000010; BEGINIF XUAN=01 THENIF CLR=1 THENCURRENT_STATE LIGHT=ZZZZZZZZ; CURRENT_STATE LIGHT=L1; CURRENT_STATE LIGHT=L2; CURRENT_STATE LIGHT=L3; CURRENT_STATE LIGHT=L4; CURRENT_STATE LIGHT=L5; CURRENT_STATE LIGHT=L6; CURRENT_STATE=S1;EN

10、D CASE;END IF;END IF; END PROCESS; LED1=LIGHT;END ART;3.3花樣二模塊 -用分頻器分頻后的時(shí)鐘來顯示花樣實(shí)現(xiàn) -實(shí)現(xiàn)淡入淡出效果LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY hy2 IS PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY hy2;ARCHITECTURE ART OF h

11、y2 IS -設(shè)計(jì)狀態(tài)機(jī),實(shí)現(xiàn)花樣轉(zhuǎn)換 TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16); SIGNAL CURRENT_STATE:STATE; SIGNAL LIGHT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(CLR,CLK1,XUAN)IS -定義花樣(1為燈亮,0為燈滅) CONSTANT L1:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000000; CONSTANT L2:STD_LOGIC_VECTOR(7 DOWN

12、TO 0):=10000000; CONSTANT L3:STD_LOGIC_VECTOR(7 DOWNTO 0):=11000000; CONSTANT L4:STD_LOGIC_VECTOR(7 DOWNTO 0):=11100000; CONSTANT L5:STD_LOGIC_VECTOR(7 DOWNTO 0):=11110000; CONSTANT L6:STD_LOGIC_VECTOR(7 DOWNTO 0):=11111000; CONSTANT L7:STD_LOGIC_VECTOR(7 DOWNTO 0):=11111100; CONSTANT L8:STD_LOGIC_V

13、ECTOR(7 DOWNTO 0):=11111110; CONSTANT L9:STD_LOGIC_VECTOR(7 DOWNTO 0):=11111111; CONSTANT L10:STD_LOGIC_VECTOR(7 DOWNTO 0):=01111111; CONSTANT L11:STD_LOGIC_VECTOR(7 DOWNTO 0):=00111111; CONSTANT L12:STD_LOGIC_VECTOR(7 DOWNTO 0):=00011111; CONSTANT L13:STD_LOGIC_VECTOR(7 DOWNTO 0):=00001111; CONSTAN

14、T L14:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000111; CONSTANT L15:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000011; CONSTANT L16:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000001; BEGINIF XUAN=10 THENIF CLR=1 THENCURRENT_STATE LIGHT=ZZZZZZZZ; CURRENT_STATE LIGHT=L1; CURRENT_STATE LIGHT=L2; CURRENT_STATE LIGHT=L3; CURRENT_STATE

15、 LIGHT=L4; CURRENT_STATE LIGHT=L5; CURRENT_STATE LIGHT=L6; CURRENT_STATE LIGHT=L7; CURRENT_STATE LIGHT=L8; CURRENT_STATE LIGHT=L9; CURRENT_STATE LIGHT=L10; CURRENT_STATE LIGHT=L11; CURRENT_STATE LIGHT=L12; CURRENT_STATE LIGHT=L13; CURRENT_STATE LIGHT=L14; CURRENT_STATE LIGHT=L15; CURRENT_STATE LIGHT

16、=L16; CURRENT_STATE=S1;END CASE;END IF;END IF; END PROCESS; LED2=LIGHT;END ART;3.4花樣三模塊 -用分頻器分頻后的時(shí)鐘來顯示花樣實(shí)現(xiàn) -從左至右逐個(gè)亮，在從右到左逐個(gè)亮LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY hy3 IS PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END

17、 ENTITY hy3;ARCHITECTURE ART OF hy3 IS -設(shè)計(jì)狀態(tài)機(jī),實(shí)現(xiàn)花樣轉(zhuǎn)換 TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14); SIGNAL CURRENT_STATE:STATE; SIGNAL LIGHT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(CLR,CLK1,XUAN)IS -定義花樣(1為燈亮,0為燈滅) CONSTANT L1:STD_LOGIC_VECTOR(7 DOWNTO 0):=10000000; CONSTANT L

18、2:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000000; CONSTANT L3:STD_LOGIC_VECTOR(7 DOWNTO 0):=00100000; CONSTANT L4:STD_LOGIC_VECTOR(7 DOWNTO 0):=00010000; CONSTANT L5:STD_LOGIC_VECTOR(7 DOWNTO 0):=00001000; CONSTANT L6:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000100; CONSTANT L7:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000010

19、; CONSTANT L8:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000001; CONSTANT L9:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000010; CONSTANT L10:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000100; CONSTANT L11:STD_LOGIC_VECTOR(7 DOWNTO 0):=00001000; CONSTANT L12:STD_LOGIC_VECTOR(7 DOWNTO 0):=00010000; CONSTANT L13:STD_LOGIC_VECTOR(7 DOW

20、NTO 0):=00100000; CONSTANT L14:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000000; BEGINIF XUAN=11 THENIF CLR=1 THENCURRENT_STATE LIGHT=ZZZZZZZZ; CURRENT_STATE LIGHT=L1; CURRENT_STATE LIGHT=L2; CURRENT_STATE LIGHT=L3; CURRENT_STATE LIGHT=L4; CURRENT_STATE LIGHT=L5; CURRENT_STATE LIGHT=L6; CURRENT_STATE LIGHT=L7

21、; CURRENT_STATE LIGHT=L8; CURRENT_STATE LIGHT=L9; CURRENT_STATE LIGHT=L10; CURRENT_STATE LIGHT=L11; CURRENT_STATE LIGHT=L12; CURRENT_STATE LIGHT=L13; CURRENT_STATE LIGHT=L14; CURRENT_STATE=S1;END CASE;END IF;END IF; END PROCESS; LED3=LIGHT;END ART;3.5頂層設(shè)計(jì) -將以上幾個(gè)模塊整合起來,實(shí)現(xiàn)八路彩燈的花樣控制LIBRARY IEEE;USE IEE

22、E.STD_LOGIC_1164.ALL;ENTITY caideng IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY caideng;ARCHITECTURE ART OF caideng IS COMPONENT fenpinqi -對(duì)分頻器模塊進(jìn)行定義 PORT( CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; CLK1:OUT STD_LOGIC); E

23、ND COMPONENT fenpinqi; COMPONENT hy1 -對(duì)花樣一模塊進(jìn)行定義 PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT hy1; COMPONENT hy2 -對(duì)花樣二模塊進(jìn)行定義 PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED2:OU

24、T STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT hy2; COMPONENT hy3 -對(duì)花樣三模塊進(jìn)行定義 PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT hy3;SIGNAL S:STD_LOGIC; -定義中間變量SIGNAL L1:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL L2:STD_LOGIC

25、_VECTOR(7 DOWNTO 0); SIGNAL L3:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN U1:fenpinqi PORT MAP(CLK,CLR,S); -對(duì)分頻器模塊進(jìn)行例化U2:hy1 PORT MAP(S,CLR,XUAN,L1); -對(duì)花樣一模塊進(jìn)行定義U3:hy2 PORT MAP(S,CLR,XUAN,L2); -對(duì)花樣二模塊進(jìn)行例化U4:hy3 PORT MAP(S,CLR,XUAN,L3); -對(duì)花樣三模塊進(jìn)行例化LED=L1 WHEN XUAN=01 ELSE -讓LED顯示選定的花樣 L2 WHEN XUAN=10 ELSE L

26、3;END ART;4. 仿真圖4.1分頻器仿真波形CLK為輸入，是機(jī)器時(shí)鐘。上升沿有效CLR為輸入，是異步復(fù)位端，當(dāng)為高電平時(shí)有效，CLK1保持狀態(tài)CLK1為輸出，是分頻后得到的我們需要的時(shí)鐘，周期是原時(shí)鐘的十六倍4.2花樣一仿真波形CLK1為輸入，是分頻后得到的時(shí)鐘CLR為輸入，是異步復(fù)位端，當(dāng)為高電平時(shí)有效XUAN是輸入，進(jìn)行選擇花樣.此時(shí)選擇的是花樣一LED1是輸出,用來顯示花樣實(shí)現(xiàn)從兩邊向中間亮，再從中間向兩邊亮,運(yùn)行結(jié)果正確4.3花樣二仿真波形CLK1為輸入，是分頻后得到的時(shí)鐘CLR為輸入，是異步復(fù)位端，當(dāng)為高電平時(shí)有效XUAN是輸入，進(jìn)行選擇花樣.此時(shí)選擇的是花樣二LED1是輸出,用來顯示花樣實(shí)現(xiàn)淡入淡出效果,運(yùn)行結(jié)果正確4.4花樣三仿真波形CLK1為輸入，是分頻后得到的時(shí)鐘CLR為輸入，是異步復(fù)位端，當(dāng)為高電平時(shí)有效XUAN是輸入，進(jìn)行選擇花樣.此時(shí)選擇的是花樣二LED1是輸出,用來顯示花樣從左