EDA課后答案(適用于朱正偉《EDA技術(shù)及應(yīng)用》)

1、11.1、設(shè)計集成計數(shù)器 74161，設(shè)計要求如下：4-BIT BINARY UP COUNTER WITH SYNCHRONOUS LOAD AND ASYNCHRONOUS CLEAR NOTEINPUTS： CLKLDNCLRNDCBAOUTPUTS：QD QC QB QA RCO*RCO = QD & QC & QB & QA LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT( CLK,LDN,CLRN : IN STD_LOGI

2、C; D,C,B,A : IN STD_LOGIC; CARRY : OUT STD_LOGIC; QD,QC,QB,QA : OUT STD_LOGIC );END;ARCHITECTURE A OF CNT4 IS SIGNAL DATA_IN: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN DATA_IN0); ELSIF CLKEVENT AND CLK=1 THEN IF LDN=0 THEN CNT:=DATA_IN; ELSE CNT:=CNT+1; END IF; END IF; CASE CNT IS WHEN 1111= CARRY CARRY=0;

3、 END CASE; QA=CNT(0); QB=CNT(1); QC=CNT(2); QD=CNT(3); END PROCESS; END A;1.2、設(shè)計一個通用雙向數(shù)據(jù)緩沖器，要求緩沖器的輸入和輸出端口的位數(shù)可以由參數(shù)決定。設(shè)計要求：N BIT 數(shù)據(jù)輸入端口 A，B。工作使能端口 EN=0 時2雙向總線緩沖器選通，DIR=1，則 A=B；反之 B=A。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY BIDIR ISGENERIC(N:INTEGER:=8); PORT(A,B :INOUT STD_LOGIC_VECTOR(N-1 DOW

4、NTO 0); EN,DIR:IN STD_LOGIC);END;ARCHITECTURE A OF BIDIR ISBEGIN PROCESS(EN,DIR) BEGIN IF EN=0 THEN AZ); BZ); ELSE IF DIR=1 THEN B=A; ELSE A=B; END IF; END IF;END PROCESS;END A;2.1、用 VHDL 語言編程實現(xiàn)十進制計數(shù)器，要求該計數(shù)器具有異步復(fù)位、同步預(yù)置功能。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT_10_2 ISPORT( CLK,CLR : IN S

5、TD_LOGIC; COUNT : OUT STD_LOGIC );END;ARCHITECTURE A OF CNT_10_2 IS SIGNAL CNT_10 : INTEGER RANGE 0 TO 10;BEGIN PROCESS(CLK,CLR) BEGIN IF CLR=1 THEN CNT_10=0; ELSIF CLKEVENT AND CLK=1 THEN CNT_10=CNT_10+1; IF CNT_10=9 THEN CNT_10=0; COUNT=1; ELSE3 COUNT=0; END IF; END IF; END PROCESS;END A;2.2、設(shè)計實現(xiàn)一

6、位全減器。行為描述行為描述: : F_SUB4F_SUB4LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB4 ISPORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB4 ISBEGIN DIFF=A XOR B XOR CIN; COUT=(NOT A AND B) OR (NOT A AND CIN) OR (B AND CIN);END A;數(shù)據(jù)流描述數(shù)

7、據(jù)流描述 F_SUB1F_SUB1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB1 ISPORT( A,B :IN STD_LOGIC; CIN :IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB1 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN S DIFF=0;COUT DIFF=1;COUT DIFF=1;COUT DIFF=0;C

8、OUT DIFF=1;COUT DIFF=0;COUT DIFF=0;COUT DIFF=1;COUT DIFF=X;COUT=X; END CASE; END PROCESS;END A;數(shù)據(jù)流描述數(shù)據(jù)流描述F_SUB2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB2 ISPORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB2 ISSIGNAL S :S

9、TD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN S=CIN&A&B; DIFF=C(1); COUT=C(0); C=00 WHEN S=000 ELSE 11 WHEN S=001 ELSE 10 WHEN S=010 ELSE 00 WHEN S=011 ELSE 11 WHEN S=100 ELSE 01 WHEN S=101 ELSE 00 WHEN S=110 ELSE 11 ;END A;數(shù)據(jù)流描述數(shù)據(jù)流描述 F_SUB3F_SUB3LIBRARY IEEE;USE I

10、EEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB3 ISPORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB3 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);5BEGIN S=CIN&A&B; DIFF=C(1); COUT=C(0); WITH S SELECT

11、C=00 WHEN 000, 11 WHEN 001, 10 WHEN 010, 00 WHEN 011, 11 WHEN 100, 01 WHEN 101, 00 WHEN 110, 11 WHEN OTHERS;END A;3.1、閱讀教材 P181 頁，例5-55并回答下列問題：（1） 、該程序的功能是什么？（2） 、請寫出該程序所有端口的功能描述。3.2、試描述一個十進制BCD 碼編碼器，輸出使能為低電平有效。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY BIN_BCD ISPORT( BIN : IN INTEGER RANGE 0

12、TO 20; -ENA : IN STD_LOGIC; BCD_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END;ARCHITECTURE A OF BIN_BCD ISBEGINBINARY_BCD : BLOCKBEGINBCD_OUT =00000000 WHEN BIN = 0 ELSE00000001 WHEN BIN = 1 ELSE00000010 WHEN BIN = 2 ELSE00000011 WHEN BIN = 3 ELSE00000100 WHEN BIN = 4 ELSE00000101 WHEN BIN = 5 ELSE00

13、000110 WHEN BIN = 6 ELSE00000111 WHEN BIN = 7 ELSE00001000 WHEN BIN = 8 ELSE00001001 WHEN BIN = 9 ELSE00010000 WHEN BIN = 10 ELSE00010001 WHEN BIN = 11 ELSE00010010 WHEN BIN = 12 ELSE00010011 WHEN BIN = 13 ELSE00010100 WHEN BIN = 14 ELSE600010101 WHEN BIN = 15 ELSE00010110 WHEN BIN = 16 ELSE00010111

14、 WHEN BIN = 17 ELSE00011000 WHEN BIN = 18 ELSE00011001 WHEN BIN = 19 ELSE00100000 WHEN BIN = 20 ELSE 00000000;END BLOCK;END A;4.1、讀教材 P151 頁，例5-32的程序，并回答以下問題：（1）請畫出該程序所描述的電路結(jié)構(gòu)圖，要求標(biāo)清楚每一個端口以及內(nèi)部信號。 （串入/串出移位寄存器）4.2、用 VHDL 語言設(shè)計一個能夠?qū)崿F(xiàn)任意整數(shù)進制的計數(shù)器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;-*ENTITY FREQDV_N IS

15、 GENERIC(N:INTEGER:=6); PORT( CLK :IN STD_LOGIC; CLK_DIV : OUT STD_LOGIC );END;ARCHITECTURE A OF FREQDV_N IS SIGNAL CNT : INTEGER RANGE 0 TO N;BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN IF CNT=0 THEN CNT=N-1; CLK_DIV=1; ELSE CLK_DIV=0; CNT=CNT-1; END IF; END IF; END PROCESS;7END A;5.1、設(shè)計一個序列信

16、號發(fā)生器，要求能夠循環(huán)輸出序列“01101001” 。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY RS_1 ISPORT( CP,S,R : IN STD_LOGIC; Q,NQ : OUT STD_LOGIC );END;ARCHITECTURE A OF RS_1 ISSIGNAL S1,R1,Q1,NQ1:STD_LOGIC;BEGIN S1=S NAND CP; R1=R NAND CP; Q1=S1 NAND NQ1; NQ1=R1 NAND Q1; Q=Q1; NQ=

17、NQ1;END A;5.2、設(shè)計一個帶復(fù)位端、置位端、CP 下降沿觸發(fā)的 JK 觸發(fā)器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY JKFF ISPORT( J,K,RST,CLR : IN BIT; CLK : IN BIT; Q,NQ : OUT BIT );END;ARCHITECTURE A OF JKFF ISSIGNAL Q_S,NQ_S : BIT;BEGIN PROCESS(J,K,RST,CLR,CLK) BEGIN IF RST=1 THEN Q_S=1; N

18、Q_S=0; ELSIF CLKEVENT AND CLK=0 THEN IF CLR=1 THEN Q_S=0; NQ_S=1; ELSIF J=0 AND K=1 THEN Q_S=0;8 NQ_S=1; ELSIF J=1 AND K=0 THEN Q_S=1; NQ_S=0; ELSIF J=1 AND K=1 THEN Q_S=NOT Q_S; NQ_S=NOT NQ_S; END IF; ELSE NULL; END IF; Q=Q_S; NQ=NQ_S;END PROCESS;END A;6.1、用 VHDL 語句描述一個三態(tài)輸出的雙 4 選一的數(shù)據(jù)選擇器，其地址信號共用，且各有

19、一個低電平有效的使能端。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DUAL_MUX_41 ISPORT( A,B,C,D : IN STD_LOGIC; ENA_N,ENB_N : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0); OUTA,OUTB : OUT STD_LOGIC );END;ARCHITECTURE A OF DUAL_MUX_41 IS SIGNAL P,Q : STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN P=ENA_N & S; Q

20、=ENB_N & S; WITH P SELECT OUTA=A WHEN 000, B WHEN 001, C WHEN 010, D WHEN 011, Z WHEN OTHERS; WITH Q SELECT OUTB=A WHEN 000, B WHEN 001, C WHEN 010, D WHEN 011, Z WHEN OTHERS; END A;6.2、用并行信號賦值語句實現(xiàn) 38 譯碼器。LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;9 ENTITY DECODER38 IS PORT(A,B,C,G1,G1A,A2B:IN ST

21、D_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END DECODER38; ARCHITECTURE BEHAVE38 OF DECODER38 IS SIGNAL INDA: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN INDAQQQQQQQQQ=XXXXXXXX; END CASE; ELSE Q=11111111; END IF; END PROCESS;END BEHAVE38;7.1、用并行信號賦值語句實現(xiàn) 8 選一數(shù)據(jù)選擇器，要求有工作使能端。LIBRARY IEEE; USE IEEE.STD_LOGIC_1

22、164.ALL; ENTITY MUX8 IS PORT(D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC_VECTOR(7 DOWNTO 0); S0,S1,S2:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END MUX8;ARCHITECTURE BEHAVE OF MUX8 IS SIGNAL S: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN S =S2&S1&S0; WITH S SECLECT D =D0 WHEN 000, D1 WHEN 001, D2 WH

23、EN 010, D3 WHEN 011, D4 WHEN 100, D5 WHEN 101,10 D6 WHEN 110, D7 WHEN 111, XWHEN OTHERS;END BEHAVE;7.2、用 VHDL 語言設(shè)計實現(xiàn)輸出占空比為 50%的 1000 分頻器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DIV_1000 ISPORT( CLK ,CLR: IN STD_LOGIC; DIV : OUT STD_LOGIC );END;ARCHITECTURE A OF DIV_1000 ISSIGNAL Q : STD_LOGI

24、C;BEGIN DIV=Q; PROCESS(CLK,CLR) VARIABLE CNT : INTEGER RANGE 0 TO 499; BEGIN IF CLR=1 THEN CNT:=0; Q=0; ELSIF RISING_EDGE(CLK) THEN IF CNT=499 THEN CNT:=0; Q=NOT Q; ELSE CNT:=CNT+1; END IF; END IF; END PROCESS;END A;8.1、設(shè)計一個一位全減器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.A

25、LL;ENTITY F_SUB3 ISPORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB3 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN11 S=CIN&A&B; DIFF=C(1); COUT=C(0); WITH S SELECT C=00 WHEN 000, 11 WHEN 001, 10 WHEN 010, 00 WHEN 01

26、1, 11 WHEN 100, 01 WHEN 101, 00 WHEN 110, 11 WHEN OTHERS;END A;8.2、用元件例化語句描述一個四位的全減器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB4_1 ISPORT( A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); CIN : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC

27、 );END;ARCHITECTURE A OF F_SUB4_1 ISCOMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END COMPONENT;SIGNAL C :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN U1: F_SUB1 PORT MAP(A(0),B(0),CIN,DIFF(0),C(0); U2: F_SUB1 PORT MAP(A(1),B(1),C(0),DIFF(1),C(1); U3: F_SUB1 PORT MAP(A(2),B(2)

28、,C(1),DIFF(2),C(2); U4: F_SUB1 PORT MAP(A(3),B(3),C(2),DIFF(3),C(3); COUT=C(3);END A;9.1、利用生成語句描述一個由 N 個一位全減器構(gòu)成的 N 位減法器，N 的默認值為 4。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB4_2 IS12GENERIC (N : INTEGER := 4);PORT( A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); CIN

29、 : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); COUT: OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB4_2 ISCOMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END COMPONENT;SIGNAL C :STD_LOGIC_VECTOR(N DOWNTO 0);BEGIN C(0)=CIN; N1: FOR I IN 0 TO N-1 GENERATE U1: F_S

30、UB1 PORT MAP(A(I),B(I),C(I),DIFF(I),C(I+1); END GENERATE; COUT=C(N);END A;9.2、設(shè)計一個模為 60、具有異步復(fù)位、同步置數(shù)功能的 8421 碼計數(shù)器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT_60 ISPORT( CLK ,CLR,PST: IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(5 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(

31、5 DOWNTO 0); CO: OUT STD_LOGIC );END;ARCHITECTURE A OF COUNT_60 ISSIGNAL CNT: STD_LOGIC_VECTOR(5 DOWNTO 0);BEGIN Q=CNT; PROCESS(CLK,CLR,PST,A) BEGIN IF CLR=1 THEN CNT0); CO=0; ELSIF RISING_EDGE(CLK) THEN IF PST=1 THEN CNT=A;13 ELSIF CNT=59 THEN CNT0); CO=1; ELSE CNT=CNT+1; CO6,M=10) PORT MAP(A=TRIGG

32、ER_IN,CLK=CLK,Y=MONO_OUT);END A;10.2、設(shè)計實現(xiàn)一個 83 優(yōu)先編碼器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MONO_TRIGGER IS -非可重復(fù)觸發(fā)單穩(wěn)態(tài)觸發(fā)器GENERIC(N:INTEGER:=5; -單穩(wěn)態(tài)定時參數(shù) M:INTEGER:=10); -定義定時參數(shù)取值范圍PORT( A,CLK: IN STD_LOGIC; Y : OUT STD_LOGIC );END;14ARCHITECTURE A OF MONO_TRIG

33、GER ISTYPE STATE IS(ST0,ST1,ST2);SIGNAL CURRENT_STATE,NEXT_STATE : STATE;SIGNAL Q:STD_LOGIC;BEGIN REG:PROCESS(A,CLK) BEGIN IF CLKEVENT AND CLK=1 THEN CURRENT_STATE IF A=0 THEN NEXT_STATE=ST0; Y=0; ELSE NEXT_STATE IF Q=1 THEN NEXT_STATE=ST2; Y=0; ELSE NEXT_STATE=ST1; Y IF A=1 THEN NEXT_STATE=ST2; Y=0

34、; ELSE NEXT_STATE=ST0; Y NEXT_STATE=ST0; END CASE; END PROCESS; AUX_COUNT:PROCESS(CURRENT_STATE,CLK) VARIABLE COUNT : INTEGER RANGE 0 TO M; BEGIN IF CLKEVENT AND CLK=1 THEN IF CURRENT_STATE/=ST1 THEN COUNT:=N; ELSE COUNT:=COUNT-1; END IF; END IF;15 IF COUNT=0 THEN Q=1; ELSE Q=0; END IF; END PROCESS;

35、END A;10-19LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CODE_PAN ISPORT( X,RST,CLK : IN STD_LOGIC; Y : OUT STD_LOGIC );END;ARCHITECTURE A OF CODE_PAN ISSIGNAL Q :STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN PROCESS(CLK,X,RST) BEGIN IF RST=1 THEN Q0); ELSIF CLKEVENT AND CLK=1 THEN Q(0)=X; Q(1)=Q(0); Q(2)=Q(

36、1); Q(3)=Q(2); Q(4)=Q(3); Q(5)=Q(4); Q(6)=Q(5); END IF; END PROCESS; WITH Q SELECT Y=1 WHEN 1110010, 0 WHEN OTHERS;END A; 8-3 優(yōu)先編碼器(when-else 實現(xiàn))：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY CODER ISPORE( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); OUTPUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );END CODER;16 A

37、RCHITECTURE ART1 ISBEGIN OUTPUT=000 WHEN D(7)=0 ELSE 001 WHEN D(6)=0 ELSE 010 WHEN D(5)=0 ELSE 011 WHEN D(4)=0 ELSE 100 WHEN D(3)=0 ELSE 101 WHEN D(2)=0 ELSE 110 WHEN D(1)=0 ELSE 111;END ART1;3.5 四選一多路選擇器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MAX4_1 ISPORT(A,B,C,D,S1,S2 : IN STD_LOGIC; Y :

38、OUT STD_LOGIC);END ENTITY MAX4_1;ARCHITECTURE HF1 OF MAX4_1 ISSIGNAL SS : STD_LOGIC_VECTOR (0 TO 1);BEGINSS Y Y Y Y NULL;END CASE;END PROCESS;END HF1;3.6 設(shè)計一個 7 人表決電路，參加表決者 7 人，同意為 1，不同意為0，同意者過半則表決通過，綠指示燈亮；表決不通過則紅指示燈亮。17設(shè)計思路設(shè)計思路：根據(jù) 7 人表決電路設(shè)計要求，7 人中至少有 4 個通過才可以表決通過，故可以在程序中設(shè)置一個變量 TEMP，使其在表決電路中遇 1 則加 1

39、，遇 0則加 0（設(shè)計中 1 表示通過，0 表示不通過） 。當(dāng) TEMP=4 時，表示表決通過，當(dāng) TEMPOUTPUTOUTPUT=1; END CASE ; END PROCESS; END BEHAVE;4-7 給出 1 位全減器的 VHDL 描述,要求:首先設(shè)計 1 位半減器,然后用例化語句將它們連接起來。設(shè) X 為被減數(shù)，Y 為減數(shù)，DIFF 是輸出差(DIFF=X-Y),SUB_OUT 是借位輸出(SUB_OUT=1,XY),SUB_IN 是借位輸入。(1.1)：實現(xiàn) 1 位半減器 H_SUBER(DIFF=X-Y；S_OUT=1,XY)LIBRARY IEEE; -半減器描述(1

40、):布爾方程描述方法 USE IEEE.STD_LOGIC_1164.ALL; ENTITY H_SUBER IS PORT( X,Y: IN STD_LOGIC; DIFF,S_OUT: OUT STD_LOGIC); END ENTITY H_SUBER; ARCHITECTURE HS1 OF H_SUBER IS18 BEGIN DIFF = X XOR (NOT Y); S_OUT XIN,Y=YIN, DIFF=A, S_OUT=B); U2:H_SUBER PORT MAP(X=A, Y=SUB_IN, DIFF=DIFF_OUT,S_OUT=C); SUB_OUT = C OR

41、 B;END ARCHITECTURE FS1;二進制全加器，元件聲明與元件例化（二進制全加器，元件聲明與元件例化（COMPONENT,PORTCOMPONENT,PORT MAPMAP）/或門LIBRARY IEEE; ；USE IEEE.STD_LOGIC_1164.ALL;ENTITY OR2A ISPORT(A,B : IN STD_LOGIC; C : OUT STD_LOGIC);END OR2A;ARCHITECTURE ART1 OF OR2A ISBEGIN C=A OR B;END ART1;/半加器；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164

42、.ALL;ENTITY H_ADDER IS PORT(A,B : IN STD_LOGIC; CO,SO: OUT STD_LOGIC);END H_ADDER;19ARCHITECTURE ART2 OF H_ADDER ISBEGIN SO = A XOR B; CO E,B=CIN,CO=F,SO=SUM);U3:OR2A PORT MAP(D,F,COUT);END ART3;10 進制異步復(fù)位計數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT_10_2 ISPORT( CLK,CLR : IN STD_LOGIC; COUN

43、T : OUT STD_LOGIC );END;ARCHITECTURE A OF CNT_10_2 IS SIGNAL CNT_10 : INTEGER RANGE 0 TO 10;BEGIN PROCESS(CLK,CLR) BEGIN IF CLR=1 THEN CNT_10=0; ELSIF CLKEVENT AND CLK=1 THEN20 CNT_10=CNT_10+1; IF CNT_10=9 THEN CNT_10=0; COUNT=1; ELSE COUNT=0; END IF; END IF; END PROCESS;END A;10 進制異步復(fù)位可調(diào)占空比LIBRARY

44、IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT_10_1 ISPORT( CLK,CLR : IN STD_LOGIC; COUNT : OUT STD_LOGIC );END;ARCHITECTURE A OF CNT_10_1 ISBEGIN PROCESS(CLK,CLR) VARIABLE CNT_10 : INTEGER RANGE 0 TO 10; BEGIN IF CLR=1 THEN CNT_10:=0; ELSIF CLKEVENT AND CLK=1 THEN CNT_10:=CNT_10+1; IF CNT_10=10 THEN C

45、NT_10:=0; COUNT=1; ELSE COUNT=0; END IF; END IF; END PROCESS;END A;10 進制同步復(fù)位計數(shù)器（用信號）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT_10_2 ISPORT( A : IN INTEGER RANGE 0 TO 10; CLK,CLR,PST : IN STD_LOGIC; COUNT : OUT STD_LOGIC );END;21ARCHITECTURE A OF CNT_10_2 IS SIGNAL CNT_10: INTEGER RANGE 0 TO

46、 9;BEGIN PROCESS(CLK,CLR,PST) -VARIABLE CNT_10 : INTEGER RANGE 0 TO 9; BEGIN IF CLR=1 THEN CNT_10=0; ELSIF CLKEVENT AND CLK=1 THEN IF PST=1 THEN CNT_10=A; ELSIF CNT_10=9 THEN CNT_10=0; COUNT=1; ELSE COUNT=0; CNT_10=CNT_10+1; END IF; END IF; END PROCESS;END A;N 位全減器LIBRARY IEEE;USE IEEE.STD_LOGIC_116

47、4.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB4_2 ISGENERIC (N : INTEGER := 4);PORT( A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); CIN : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); COUT: OUT STD_LOGIC );END;ARCHITECTURE A OF F_SUB4_2 ISCOMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIF

48、F,COUT : OUT STD_LOGIC ); END COMPONENT;SIGNAL C :STD_LOGIC_VECTOR(N DOWNTO 0);BEGIN C(0)=CIN; N1: FOR I IN 0 TO N-1 GENERATE U1: F_SUB1 PORT MAP(A(I),B(I),C(I),DIFF(I),C(I+1); END GENERATE; COUT=C(N);22END A;帶異步復(fù)位的能自啟動的 4 位 l 環(huán)形計數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY HUANXINGJISHU IS PORT(CLK,RS:IN STD_LOGIC; COUNTOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END HUANXINGJISHU;ARCHITECTURE BEHAVE OF HUANXINGJISHU IS SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);