EDA程序改錯題

1、程序改錯題1.已知sei為STD_L0GIC_VECT0R(1 DOWNTO 0)類型的信號，而a b、c、d、q均為STD_LOGIC類型的信號，請判斷下面給出的CASE語句程序片段：CASE sei ISWHE “N 00”=qqqq=d；END CASE；答案：CASE語句缺“WHEN OTHERS語句。2.已知datan1, data為STD_LOGIC_VECTOR(15 DOWNTO 0)類型 的輸入端口，data_out為STD_LOGIC_VECTOR(15 DOWNTO 0)類型的輸出端 口，add_sub為STD_LOGIC類型的輸入端口，請判斷下面給出的程序片段：LIBR

2、ARYlEEE；USE IEEE.STD_LOGIC_1164.ALL；ENTITY add ISPORT(data_in1 , data_in2 : IN INTEGER；data_out : OUT INTEGER):END add；ARCHTECTURE add_arch OF add ISCONSTANT a:INTEGER=2；BEGINdata_out=( datajn1+ datajn2) * a；END addsub_arch；答案：常量聲明時賦初值的“ v 符號應(yīng)改用“:=”符號。3已知Q為STD_LOGIC類型的輸出端口，請判斷下面的程序片段：ARCHITECTURE te

3、st_arch OF test ISBEGINSIGNAL B : STD_LOGIC；Q= B；END test_arch答案：信號SIGNAL的聲明語句應(yīng)該放在BEGIN語句之前。4已知A和Q均為BIT類型的信號，請判斷下面的程序片段：ARCHITECTURE archtest OF test ISBEGINCASE A ISWHENQQv=4: 0*END CASE；END archtest；答案：CASE語句應(yīng)該存在于進程PROCESS內(nèi)。三.判斷改錯題（3 分 X 6 題）（評分標準：給出正確答案1 分/題；答案基本正確 0.5 分/題。）1 已知 A 和 Q 均為 BIT 類型的信

4、號，請判斷下面的程序片斷：ARCHITECTURE test OF test ISBEGINCASE A ISWHENV =QQv=O ；END CASE ；END test ；【參考答案】：CASE 語句應(yīng)該存在于進程 PROCESS 內(nèi)。2 已知 start 為 STD_LOGIC 類型的信號，sum 是 INTEGER 類型的信號，請判斷下面的程序片 斷：PROCESS （start）BEGINFOR i IN 1 TO 9 LOOPsum := sum + i ;END LOOP ;END PROCES；S【參考答案】：sum 是信號，其賦值符號應(yīng)該由改為“ v=”。3已知 Q 為 S

5、TD_LOGIC 類型的輸出端口，請判斷下面的程序片斷：ARCHITECTURE test OFtest ISBEGINSIGNAL B : STD_LOGIC :END test ;【參考答案】：信號 SIGNAL 的申明語句應(yīng)該放在 BEGIN 語句之前。4 -已知 A 和 B 均為 STD_LOGIC 類型的信號請判斷下面的語句：Bv=x；【參考答案】：不定態(tài)符號應(yīng)該由小寫的X，改為大寫的X，。5.已知 A 為 INTEGER 類型的信號，B 為 STD_LOGIC 類型的信號，請判斷下面的程序片斷：ARCHITECTURE test OF test ISBEGINB v r?n”、一w

6、qWHEN “11=dq?ENDCASE；鄉(xiāng)專合條】-CASE語句“ WHEN OTHER語句。四、判斷下面程序中是否有錯誤，若有錯誤請改正；1、SIGNAL A,EN:STD_LOGIC; PROCESS(A,EN)VARIABLE B:STD_LOGIC;BEGINIFEN=411THENB=A;END ;END PROCESS;2、RCHITECTURE ONE OF SAMPLE IS VARIABLE A，B，C：INTEGER；BEGINBv=x；Cv=A+B；END ;五、判斷下列程序是否有錯誤，如有則指出錯誤所在(10分)程序:LIBRARY IEEE;USE IEEE.STD

7、_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY zyt12 ISPORT(R,EN,CP: IN bit;Q: BUFFER STD_LOGIC_VECTOR(0 D0WNT0 3);CO: OUT STD_LOGIC);END zyt;ARCHITECTURE c10 OF zyt12BEGINC0=*1 * WHEN(EN=*1 * AND Q=1011H) ELSE；O;PROCESS(R,CP)BEGINIFR=TTHENQv=”0000”；ELSIF (CPEVEN

8、T AND CPv=T) THENIF EN=V THENQ=Q;ELSIF Q=H1011 THENQ= 00001;ELSEQ:=Q+1;END IF;END PROCESS;END one;仔細閱讀下列程序，回答問題LIBRARY IEEE;-1USE IEEE.STD_LOGIC_1164.ALL;-2ENTITY LED7SEG IS-3PORT (A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);一4CLK : IN STD_LOGIC;-5LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);-6END LED7SEG;- 7ARC

9、HITECTURE one OF LED7SEG IS一8SIGNAL TMP : STD_LOGIC;一9BEGIN一10SYNC : PROCESS(CLK, A)-11BEGIN12IF CLKEVENT AND CLK = T THEN- 13TMP LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S = 00000001、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4B ISPORT

10、(CLK，RST，ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT4B;ARCHITECTURE behav OF CNT4B ISSIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK, RST, ENA)BEGINIF RST = T THEN CQI = 0000：ELSIF CLKEVENT AND CLK = T THENIF ENA =n1 ” THEN CQI = CQI + 1;ELSE C

11、QI v= ”0000”；END IF;OUTY v= CQI ;END PROCESS;COUTV=CQI(0) AND CQI(1) AND CQIAND CQI (3);END behav;2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLK_6D ISPORT (CLK,RST: IN STD_LOGIC;END IF；CLK_OUT: OUT STD_LOGIC);END CLK_6D;ARCHITECTURE

12、 ONE OF CLK 6D ISVARIABLE TEMP:STD_LOGI(SIGNALBEGINPROCESS(CLK)VARIABLE CNT6D: INTEGER RANGE 0 TO 3;CONSTANT SIGN: INTEGERS;BEGINIF (RST =“) THEN TEMP = *1 * , OELSIF CLKEVENT AND CLK-1，THEN(CLKEVENT AND CLK=T)IF (CNT6D = SIGN) THENCNT6D := 0;TEMP = NOT TEMP;ELSE CNT6D :=CNT6D+1;END IF;END IF;END PR

13、OCESS;CLK_OUT null;end case;end process;end one;4、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY cou nter ISPORT (reset: IN STD_LOGIC;clock: IN STD_LOGIC;num: buffer in teger range 0 to 3； 多一個 “ ；n)；END;ARCHITECTURE behav OF jishu ISjishu改為COunterBeg inProcess(reset,clock)Beg inIf reset二thennum=0;E

14、lsif rising_edge(clock) thenIf num=3 the nnuinv=0;elsenumv二nu m+1;end if;end process;end;少end if;5、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD LOGIC UNSIGNED:STD_LOGIC_UNSIGNED.ALLENTITY LX3 2 ISPORT(CLK,CLR,OE:IN BIT;D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q:OUT STD_L0GIC_VECT0R(7 DOWNTO 0);END

15、 LX3_2;ARCHITECTURE struc OF LX3_2 ISVARIABLE Q_TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNALBEGINPROCESS(CLR)PROCESS(CLK)BEGINIF CLR=O THEN Q TEMPv-000000001;”00000000”ELSIFCLK=TTHENQ_TEMP=D;ELSE Q_TEMPv=Q_TEMP;END IF;END PROCESS;Q=Q_TEMP WHEN OE=T ELSEEND struc;6LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD LOGIC UNSIGNED; USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY LX