Renesas V850ES

1、renesas v850esrenesas 公司的v850es-jx3 系列32位包括v850es/jc3-l系列和v850es/je3-l系列,集成了v850es cpu內(nèi)核和外設(shè)功能如rom/ram,定時(shí)器/計(jì)數(shù)器,串行接口,主要用在數(shù)碼相機(jī),電表,移動(dòng)終端,數(shù)字家用電器和其它消費(fèi)類.本文介紹了v850es-jx3 系列主要特性,方框圖,以及移動(dòng)心電圖(ecg)系統(tǒng)框圖和移動(dòng)心電圖(ecg)推舉的元件.the v850es/jx3 microcontrollers are equipped with a high-capacity memory of 1 mb. naturally fur

2、nished with functional interchangeability and pin interchangeability with the v850es/jx2 microcontrollers and capable of appropriating their development environment as well, the v850es/jx3 devices are capable of realizing system acceleration with ease.the newest arrival to the lineup is the v850es/j

3、x3-l microcontroller, an ultra-low power-consuming version of the v850es/jg2 microcontroller, with less than half of its power comsumption current. the v850es/jx3-l lineup has achieved an industry-leading nominal power/performance ratio (0.9 mw/, which comes in under the 1 mw marker according to the

4、 dhrystone evaluation) and actual operating current of 13 ma typ. (at 20 mhz) .moreover, microcontrollers built in (peripheral) function are added in this low power v850es/jx3-l product lineup.the v850es/jc3-l and v850es/je3-l are 32-bit single-chip microcontrollers that include the v850es cpu core

5、and peripheral functions such as rom/ram, timer/counters, serial interfaces, an a/d converter, a d/a converter.in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850es/jc3-l and v850es/je3-l feature multiply instructions, saturated operation instruction

6、s, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. moreover, as a real-time control system, the v850es/jc3-l and v850es/je3-l enable an extremely high cost-performance for applications that require super low powe

7、r consumption, such as pc peripheral device, ecr peripheral device, and industrial instrument.v850es-jx3 系列主要特性:minimum instruction execution time: 50 ns (operating on main clock (fxx) of 20 mhz: vdd = 2.7 to 3.6 v)200 ns (operating on main clock (fxx) of 5 mhz: vdd = 2.2 to 3.6 v)30.5 s (operating

8、on subclock (fxt) of 32.768 khz)general-purpose registers: 32 bits 32 registerscpu features: signed multiplication (16 16 32): 1 to 2 clockssigned multiplication (32 32 64): 1 to 5 clockssaturated operations (overflow and underflow detection functions included)most instructions can be executed in 1

9、clock cycle by using 32-bit risc-based 5-stage pipeline architectureinstruction fetching from internal rom and accessing internal ram for data can beexecuted separately, by using harvard architecturehigh code efficiency achieved by using variable length instructions32-bit shift instruction: 1 clock cyclebit manipulation instructionsload/store instructions with long/short formatmemory space: 64 mb