數(shù)字邏輯課程設(shè)計(jì)報(bào)告

1、多功能數(shù)字電子鐘院系：計(jì)算機(jī)與控制工程姓名：班級(jí)：學(xué)號(hào)：指導(dǎo)老師：時(shí)間：2014年6月26日星期四地點(diǎn)：工程實(shí)訓(xùn)中心目錄多功能數(shù)字電子鐘1一、系統(tǒng)功能描述3二、方案總休論述3三、頂層框框圖四、設(shè)計(jì)過(guò)程、模塊仿真及實(shí)現(xiàn)結(jié)果60進(jìn)制24進(jìn)制八選一模八計(jì)數(shù)器（刷新）87段譯碼驅(qū)動(dòng)9二選一11脈沖發(fā)生器12調(diào)時(shí)控制器13分頻器14整點(diǎn)報(bào)時(shí)器15五、實(shí)驗(yàn)結(jié)果以及心得休會(huì)17、功能描述具有二十四小時(shí)小時(shí)計(jì)時(shí)器的基本計(jì)時(shí)功能，同時(shí)具有數(shù)碼管顯示，整點(diǎn)報(bào)時(shí)，時(shí)間校準(zhǔn)的 功能。二、方法論述利用60,60,24進(jìn)制計(jì)數(shù)器模擬電了鐘的棊本計(jì)時(shí)功能，并通過(guò)八選一、模8計(jì)數(shù)器和7段 譯碼器實(shí)現(xiàn)時(shí)、分、秒在數(shù)碼管上的顯示

2、。編寫(xiě)控制端，控制分和小時(shí)的調(diào)整，達(dá)到校準(zhǔn)的 目的。編寫(xiě)分頻器實(shí)現(xiàn)報(bào)時(shí)不同聲調(diào)，并在吋、分、秒輸出而加入判斷條件，如果接近整點(diǎn) 就輸出頻率，實(shí)現(xiàn)整點(diǎn)報(bào)時(shí)功能。三、頂層框框圖四. 設(shè)計(jì)過(guò)程.模塊仿真及實(shí)現(xiàn)結(jié)果60進(jìn)制程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count_60 isport(elk:in stdjogic;clr : in stdjogic;cl,c2:out stdogic_vector(3 downto0);co:out std_logic);end cou

3、nt_60;architecture a of count_60 issignal dl,d2 : std_logic_vector(3 downto 0); beginprocess(clk)beginif(clk'event and clk='l')then訐(clr='l')then dl<="0000" d2<="0000"elseif(d2=,0101h and dl1001”)then dl<=n0000"d2<="0000" co<='

4、;l'elseif(dl=h1001")the n dl<="0000"d2<=d2+,l,;elsedl<=dl+,l,;co<='0,; end if;end if;end if;end if;end process;cl<=dl;c2<=d2;end a;模塊 l> / i1ccount_60-elk d3.o dr c23.o ooinst24進(jìn)制程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;en

5、tity count_24 isport(clk,clr : in std_logic;co: out stdjogic;cl,c2: out stdogic_vector(3 downto 0);end count 24;architecture a of count_24 issignal dl,d2 : std_logic_vector(3 downto 0);beginprocess(clk) beginif(clk'event and clk='l')then if(clr='l,)thendl<="0000"d2<=&

6、quot;0000n;elseif(d2=,0010" and dl=,0011")then dl<="0000,'d2<=h0000" co<='l'elseif(dl=n1001")the n dl<="0000"d2<=d2+,l,;elsedl<=dl+,l,；co<=,0,;end if;end if;end if;end if;end process;cl<=dl;c2<=d2;end a;模塊圖count 24clr d3.oc23.

7、oinst模塊仿真圖©auxnxw xx丫xeix乂乂乂乂xxxxx7】x乂關(guān)0dcix2dc-tuln_n_n_n_n_n_n_n_n_n_n_n_n_n_rln_n_n_mi rn八選一程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity a8_l isport(seco,secl,mino,minl,houo,houl: in stdogic_vector(3 downto 0); y: in stdogic_vector(2 downto 0);bo: out std

8、_logic_vector(3 downto 0);b,c: out stdjogic);end a8_l;architecture cc of a8_l isbeginprocess(y,seco，secl,min 0,minl ,houo,houl)begincase(y) iswhen"lll"=>b0<=sec0;b<='0'c<='0'when"110"=>b0<=secl;b<='0'c<='0,;when"101"=&

9、gt;b0<=min0;b<=,l'c<='0,;when"100"=>b0<=minl;b<=,0'c<=,0,;when,011,=>b0<=hou0;b<='l,;c<=,0,;when"010"=>b0<=houl;b<=,0'c<=,0,;when others =>bo<="oooo"b<='o'c<=,l,;end case;end process;en

10、d cc;模塊圖w3.ob片 seco3.o 泊 sect3.0 治 mino3.omin!3.0) hoik)3.0 i 泊 bout3.0 4 y2.oj:inst模塊仿真 bo-b03-b02-bol b00 ± seela： yay2>-yl>-y0>ir< 0"yj(8 x 1 x 2)( x x0x ij: 11/x8：2/ 1/35模八計(jì)數(shù)器（刷新）程序library ieee;use ieee.std_logic_1164.all;use ieee.stdogic_unsigned.all;entity xunhuan8_l is p

11、ortfclk : in stdjogic;output: out stdogic_vector(2 downto 0) );end xunhuan8_l;architecture a of xunhuan8_l issignal b : std_logic_vector(2 downto 0);beginprocess(clk)beginif(clk'event and clk=,l')thenif(b=,lll,)then b<="000h;elseb<=b+,l,; end if;end if;output<=b;end process;end

12、 a;模塊圖歹r %.4 xunhuans_1i 2elk oiftput2.0j1 一inst模塊仿真圖valu)ps10.0 ns120 眄30 9 ns40小50.0 ns60 9 ns7°小80. 0 ns90. 0 ns117.17.4nsjelk1 1 1"n r-lj_ir-l-ljljl1-noutputa(0 x1x2j r3x r5j( x x 0xtn7段譯碼驅(qū)動(dòng)程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity qudong isport(

13、 a: in stdogic_vector(3 downto 0);b,c: in stdjogic;b0,bl/b2,b3,b4/b5,b6,b7: out std_logic);end qudong;architecture haha of qudong isbeginprocess(a,c/b)beginif(c=*l')the nb0<='0,;bl<=,0'b2<=,0,;b3<=,0'b4<=,0,;b5<=,0,;b6<=,0,;b7<=b;elsecase a iswhen"0000&qu

14、ot;=>b0<='l'bl<=,l,;b2<=,l'b3<='l,;b4<=,l,;b5<=,l,;b6<=,0,;b7<=b;when "0001"=>b0<=,0,;bl<=,l,;b2<='l,;b3<=,0,;b4<=,0,;b5<=,0,;b6<=,0,;b7<=b;when"0010"=>b0<=,l'bl<='l,;b2<=,0'b3<=,

15、l,;b4<=,l,;b5<=,0'b6<=,l,;b7<=b;when,0011"=>b0<='l,;bl<=,l,;b2<='l,;b3<=,l,;b4<=,0,;b5<=,0,;b6<=,l,;b7<=b;when"0100,=>b0<=,0,;bl<='l'b2<='l,;b3<=,0'b4<='0,;b5<=,l,;b6<=,l,;b7<=b;when,0101"

16、;=>b0<=,l'bl<='0,;b2<=,l,;b3<=,l,;b4<=,0,;b5<=,l'b6<=,l'b7<=b;when"0110"=>b0<=,l'bl<=,0,;b2<='l'b3<='l,;b4<='l,;b5<='l,;b6<='l,;b7<=b;when"0111"=>b0<=,l'bl<='l,;b2&l

17、t;=,l,;b3<=,0,;b4<=,0,;b5<=,0'b6<=,0,;b7<=b;when,1000"=>b0<='l'bl<=,l,;b2<='l,;b3<=,l,;b4<=,l,;b5<=,l,;b6<=,l,;b7<=b;when,1001,=>b0<='l,;bl<='l,;b2<=,l,;b3<=,l'b4<=,0,;b5<=,l,;b6<=,l,;b7<=b;whenothe

18、rs =>b0<='l,;bl<='l'b2<='l'b3<='l'b4<='l,;b5<=,l'b6<='0,;b7<=b;end case;end if;end process;end haha;模塊圖t>4b6b7$彳模塊仿真圖vd”10.0 ns20.0 ns30.0 ns40._0 ns50.0 ns60.9 ns70j ns80.0 ns90.0 ns100.0 ns j10.0 >1117. cnsj/0)(1x 2 x )(x x 7

19、1( x 9 x-a! 172-al?rl01:rl 1ii>0i1!i>1"ir>21>311i>411.jb5t>6l1li>7i（選擇輸出器，在校時(shí)器和進(jìn)制器之間選擇是校時(shí)還是繼續(xù)進(jìn)行基本時(shí)鐘計(jì)數(shù)）程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity a2_l isport(clk,chang巳set: in stdjogic;clkl: out stdogic);end a2_l;architecture haha of a2

20、_l isbeginprocess(change)begincase set iswhen'o->-(set=,o')then clkl<=clk;when 'l'=>-elseclkl<=cha nge;end case;end process;end haha;模塊仿真圖脈沖發(fā)生器程序library ieee;use ieee.std_logic_1164.all;:in stdjogic;:in stdjogic;:out stdjogic);use ieee.std_logic_unsigned.all; entity tiao

21、isport(elkchangesetend tiao;architecture haha of tiao is beginprocess(clk)beginif(clk'event and clk='l')then if(change='l')then set<='l'elseset<='0'end if;end if;end process;end haha;模塊仿真圖調(diào)時(shí)控制器程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_uns

22、igned.all;entity kongzhi isport(set: in stdogic;change: in stdogic;changel，change2,change3: out std_logic; setl,set2,set3: out stdjogic);end kongzhi;architecture haha of kongzhi issignal reset: std_logic_vector(l downto 0);signal inl,in3n2: stdjogic;beginprocess(set,inlj n2n3jeset)begin訐(sefevent an

23、d set=,l,)thenif(reset="ll")thenreset<="oon;elsereset<=reset+,l,;end if;end if;case(reset)iswhen,00,=>inl<=,0,;in2<=,0,;in3<=,0,; when"01"=>inl<='l,;in2<=,0,;in3<=,0,;setl<=inl; when"10"=>inl<='0'in2<='l,;in

24、3<=,0,;set2<=in2; when"ll,=>inl<=,0,;in2<='0,;in3<=,l'set3<=in3; end case;setl<=in i;set2<=in2;set3<=in3;end process;process(change)beginif(inl='l*)thencha ngelv=cha nge;change2v0'cha nge3v=o; elsif(in2='l')thencha nge2v 二 cha nge;changelv 二

25、 o;cha nge3v 二,o'elsif(in3='l')thenchange3<=cha nge;change2v='0'cha ngelv="0'elsecha nge3v='0'cha nge2v=o;cha ngelv=o;end if;end process;end haha;模塊圖模塊仿真分頻器library ieee;use ieee.std_logic_1164.all;use ieee.stdogic_unsigned.all;entity fenpin isport(clk: in stdj

26、ogic;clkl,clk2 : out stdogic);end fen pin;architecture haha of fenpin is signal a : stdogic_vector(l downto 0); beginprocess(clk)beginclkl<=clk;if(clk'event and clk='l')thencase a iswhen"ll"=>clk2<=,l,;a<="00"when"10"=>clk2<='0'a<

27、;=a+,l,;when,01"=>clk2<='l'a<=a+'l,;when"00"=>clk2<='0,;a<=a+'l,;end case;end if;end process;end haha;模塊仿真圖name16.78 nselka 1clkla 1clk2a 116.775 nsjn_n_n_n -tlttm _ltl±_nrn_lm±_nnj_rlj_rn_l整點(diǎn)報(bào)時(shí)器library ieee;use ieee.std_logic_1164.all;u

28、se ieee.std_logic_unsigned.all;entity zhengdian isport(fenl,fen2,miaol,miao2: in std_logic_vector(3 downto 0);clkl,clk2: in stdjogic;elk: out stdjogic);end zhengdian;architecture haha of zhengdian isbeginprocess(clkl,clk2)beginif(fen2=h0101")thenif(fenl=h1001")thenif(miao2="0101")thenif(miaol="0101")the nclk<=clk2;elsif(miaol="0110")the nclk<=clk2;el