杭電計(jì)組實(shí)驗(yàn)四.doc

實(shí)驗(yàn)報(bào)告 2016 年 4 月 22 日 成績： 姓名學(xué)號班級14083612專業(yè)信息安全課程名稱計(jì)算機(jī)組成原理課程設(shè)計(jì)任課老師曾虹指導(dǎo)老師曾虹機(jī)位號實(shí)驗(yàn)序號實(shí)驗(yàn)名稱寄存器堆實(shí)驗(yàn)時間2016.4.22實(shí)驗(yàn)地點(diǎn)1教南實(shí)驗(yàn)設(shè)備號一、實(shí)驗(yàn)程序源代碼module Reg(LED,RW_SW,AB,Reg_Addr_A,Reg_Addr_B,Write_Reg,clk,rst); input4:0 Reg_Addr_A,Reg_Addr_B;input Write_Reg;input1:0 RW_SW;input clk;input rst;output7:0 LED;input AB;reg31:0REG_File0:31; reg7:0 LED;wire31:0 W_Data1 = 32h00000001; wire31:0 W_Data2 = 32h0000000A; wire31:0 W_Data3 = 32h00000006; wire31:0 W_Data4 = 32h00000003; wire31:0 A = REG_FileReg_Addr_A;wire31:0 B = REG_FileReg_Addr_B;integer i; always (posedge clk or posedge rst)begin if(AB) case(RW_SW) 2b00 : LED=A7:0; 2b01 : LED=A15:8; 2b10 : LED=A23:16; 2b11 : LED=A31:24; default : LED=A7:0; endcaseelse case(RW_SW) 2b00 : LED = B7:0; 2b01 : LED = B15:8; 2b10 : LED = B23:16; 2b11 : LED = B31:24; default : LED = B7:0; endcase if(rst) for(i = 0; i 32; i = i + 1) REG_Filei = 0; else begin if(Write_Reg) begin if(AB) case(RW_SW) 2b00 : REG_FileReg_Addr_A=W_Data1; 2b01 : REG_FileReg_Addr_A=W_Data2; 2b10 : REG_FileReg_Addr_A=W_Data3; 2b11 : REG_FileReg_Addr_A=W_Data4; endcase else case(RW_SW) 2b00 : REG_FileReg_Addr_B=W_Data1; 2b01 : REG_FileReg_Addr_B=W_Data2; 2b10 : REG_FileReg_Addr_B=W_Data3; 2b11 : REG_FileReg_Addr_B=W_Data4; endcase end end end endmodule二、仿真波形三、電路圖四、引腳配置（約束文件）NET Add4 LOC = T5;NET Add3 LOC = V8;NET Add2 LOC = U8;NET Add1 LOC = N8;NET Add0 LOC = M8;NET WR LOC = V9;NET C1 LOC = T9;NET C0 LOC = T10;NET clk LOC = C9;NET RS LOC = D9;NET AB LOC = A8;NET LED7 LOC = T11;NET LED6 LOC = R11;NET LED5 LOC = N11;NET LED4 LOC = M11;NET LED3 LOC = V15;NET LED2 LOC = U15;NET LED1 LOC = V16;NET LED0 LOC = U16;五、思考與探索寄存器地址寫入數(shù)據(jù)讀出數(shù)據(jù)$000000000_00000000_0000$000010000_00030000_0003$000117FFF_FFFF7FFF_FFFF$001117FFF_FFFF7FFF_FFFF$011110000_00000000_0000$111110000_00030000_0003$100007FFF_FFFF7FFF_FFFF$110007FFF_FFFF7FFF_FFFF修改后的寄存器模塊：time scale 1ns/1psMoudle Register(R_Addr_A,R_Addr_B,R_Data_A,R_Data_B,W_Addr,W_Data,Write_Reg,Clk,Reset);input 4:0 R_Addr_A;input 4:0 R_Addr_B;input 4:0 W_Addr;input 31:0 W_Data;input Write_Reg;input Clk;input Reset;output 31:0 R_Data_A;output 31:0 R_Data_B;integer i;reg31:0 REG_Files31:0;/定義寄存器assign R_Data_A=REG_FilesR_Addr_A;assign R_Data_B=REG_FilesR_Addr_B;always (posedge Clk or posedge Reset)beginif(Reset)/清零beginfor(i=0;i32;i+)REG_Filesi=0;endelsebeginif(Write_Reg&(W_Addr!=0)beginREG_FilesW_Addr=W_Data;endendendEndmoudle（3）、讀操作是時鐘的下降沿時候執(zhí)行的，