數(shù)字設(shè)計(jì) 第9章 存儲(chǔ)器、CPLD和FPGA學(xué)習(xí)課件

Chapter9Memory、CPLDandFPGA本章只要求存儲(chǔ)器中的ROM及其用于組合邏輯電路的設(shè)計(jì)2/28/20252/28/2025chapter9memoryROM(read-onlymemory)RAM(random-accessmemory)Non-volatilewhilepowereddownVolatilewhilepowereddownOftenbeusedstorefirmwareorinitialprogramofthecomputer…DataexchangeandstoringtemporarilyinCPUorothermicroprocessormemory：storebitsinastructuredway2/28/2025chapter99.1Read-OnlyMemory(ROM)1.basicstrcture2n×bROMn-bitaddressinputb-bitdataoutputA0A1A2An-2An-1D0D1Db-1……×××××D0Db-1…0…00An-1…A00…011…11××××××××××b-bitdatasketchmapofRAM2/28/2025chapter92.InternalROMstructureRow(address)decoder…A0A1An-1…storagearray

（M×b）…D0Db-1outputcircuit…01MaddressinputDataoutput2/28/2025chapter9wordline

bitlineaddressdecoder輸出電路addressinputadatastoredunitdatastoredarrayDataoutputhasdiode:store1nodiode:store08×4ROMstructure2/28/2025chapter93.Two-dimensionaldecoding128×1ROM0000000~00011110010000~00111111110000~1111111……地址2/28/2025chapter9MOStransistorsasstorageelements2/28/2025chapter94.commercialROMtypesmask-programmableROM,arrayconnectionsareprogrammedduringsemiconductormanufactureusingamask.veryfast.verydense.expensive,2-4weekturn-around,lowpowerProgrammableROM(PROM),fusestoprogramonceinthefield,usePROMprogrammer,inexpensivewordlinebitlinefuse2/28/2025chapter9EPROM（ErasablePROM）,fusesimplementedusingfloating-gateMOStransistorstoprogram10k~100ktimesinthefield,erasedbyfloodingwithUVlight.E2PROM（ElectricallyEPROM）,byte-program,individualstoredbitsmaybeerasedelectrically.flashE2PROM,aspecifictypeofE2PROMthatiserasedandprogrammedinlargeblocks2/28/2025chapter9floating-gateMOSstorageelementserasedbyUVlight2/28/2025chapter9按照數(shù)據(jù)的輸入/輸出分為串行EEPROM和并行EEPROM。串行EEPROM：在讀寫數(shù)據(jù)時(shí)，輸入/輸出時(shí)通過(guò)2線、3線、4線或SPI總線等接口方式進(jìn)行的。并行EEPROM：數(shù)據(jù)的輸入/輸出是通過(guò)并行總線進(jìn)行的。近期，低功耗，寫入/擦除速度快的產(chǎn)品很多，如Microchip公司的新型8千位、16千位串行EEPROM，最快時(shí)鐘10MHZ，寫入時(shí)間5ms，電流3mA,內(nèi)置寫保護(hù)功能，可保存數(shù)據(jù)達(dá)200年，承受100萬(wàn)次擦寫。Atmel公司的AT24C××系列……2/28/2025chapter95.UsingROMfor“random”combinationallogicfunctionsStoretheoutputvalueofagiventruthtableintheROM,thefunctioninputsareconnectedtotheaddressinput.Exp1:thedualpolaritydecoder.(P.801)POLI1I0Y3Y2Y1Y0000011100110110101101011111010010001010100110001011100018×4ROMA0A1A2D0D1D3D2POLI1I0Y0Y1Y2Y32/28/2025chapter9Exp2:4×4multiplier每行第一個(gè)數(shù)據(jù)單元的地址每行包含16個(gè)數(shù)據(jù)單元的數(shù)據(jù)2/28/2025chapter9MoreExp.:ROM在同步時(shí)序電路設(shè)計(jì)中的應(yīng)用位序列信號(hào)的產(chǎn)生：計(jì)數(shù)器—ROM法設(shè)計(jì)一個(gè)碼長(zhǎng)為8位的序列信號(hào)發(fā)生器，信號(hào)序列為01111110。CLKCLRLDENPENTDCBAQCQDQBQARCOADD2ADD1ADD0SEQVCCCLK…D0D1D2D38×4ROM2/28/2025chapter9address

QCQBQAROM中存儲(chǔ)的數(shù)據(jù)D3~D0000000000100010100001011000110000011010001110000111100002/28/2025chapter9ROM在組合電路設(shè)計(jì)中的應(yīng)用試用8×4ROM實(shí)現(xiàn)如下組合邏輯函數(shù)

F1=AB+A’C,F2=AB+B’C解：先化作標(biāo)準(zhǔn)和式

以輸入變量作為ROM的地址，將輸出值放入ROM單元。用16字×4位ROM實(shí)現(xiàn)2輸入變量的與非、或非、異或和同或

實(shí)現(xiàn)4位二進(jìn)制碼—格雷碼的轉(zhuǎn)換2/28/2025chapter9Random-accessmemory(RAM)StaticRAMDynamicRAMbotharevolatileRandomaccessmeans:locationsinthememorycanbewrittentoorreadfrominanyorder,regardlessofthememorylocationthatwaslastaccessed.storeabitofdatainthestateofaflip-flopstoreabitofdataasachargeinacapacitor2/28/2025chapter99.3StaticRandom-AccessMemory2n×bRAMstructureA0A1Din0An-2An-1D0D1Db-1…Dinb-1…CSOEWEAddressinputsDatainputsControlinputsDataoutputs×××××D0Db-1…0…00An-1…A00…011…11××××××××××CS、OE有效，b位數(shù)據(jù)輸出CS、WE有效，b位數(shù)據(jù)輸入……2/28/2025chapter9SRAMinternalstructureAddressdecoder…A0A1An-1…Storagearray

(M×b)…D0Db-1Outputcircuit…01MD0Db-1…WR/RDcontrolWE_LCS_LOE_L2/28/2025chapter9Astatic-RAMcellSEL_L、WR_Lbothnegated,Dlatchholdthedata；SEL_Lisasserted,tri-statebufferenable,dataoutput(read);SEL_L、WR_Lbothbeasserted,Dlatchopen,anewbitisstored.storeabitofdatainthestateofaflip-flop2/28/2025chapter9synchronousSRAMAbitofstorageisalsoalatch.Control,addressesandwritingorreadingdataarealloccurredattheedgeofthesameclock.2/28/2025chapter99.4dynamicRAMWrite:Chargethecapacitor---store1;Dischargethecapacitor---store0.Read:PrechargebitlinetoavoltagehalfwaybetweenHandL;SetwordlinetoH;ThecapacitorvoltageisH---bitlineispulledslightlyhigherThecapacitorvoltageisL---bitlineispulledslightlylowerstoreabitofdatainaseparatecapacitorthroughaMOStransistor,andneedtoberefreshedperiodically.2/28/2025chapter92/28/2025chapter9SDRAMControlanddataoperationsarereferencedtoacommonclocksignal.是singledatarate,與系統(tǒng)總線速度同步，在一個(gè)時(shí)鐘周期的上升沿傳輸一次數(shù)據(jù)。曾經(jīng)是PC電腦上最為廣泛應(yīng)用的一種內(nèi)存類型，分為PC66、PC100、PC133等不同規(guī)格，而規(guī)格后面的數(shù)字就代表著該內(nèi)存最大所能正常工作系統(tǒng)總線速度2/28/2025chapter9雙數(shù)據(jù)傳輸模式同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器，即DDRSDRAM(DoubleDataRateSynchronousDynamicRandomAccessMemory)是一種繼SDRAM后產(chǎn)生的內(nèi)存技術(shù)，為具有雙倍數(shù)據(jù)傳輸率之SDRAM，其數(shù)據(jù)傳輸速度為系統(tǒng)頻率之兩倍，由于速度增加，其傳輸效能優(yōu)于傳統(tǒng)的SDRAM。一個(gè)時(shí)鐘周期內(nèi)傳輸兩次次數(shù)據(jù)，它能夠在時(shí)鐘的上升期和下降期各傳輸一次數(shù)據(jù)。2/28/2025chapter9存儲(chǔ)容量的擴(kuò)展