Vivado從此開始（第2版）課件全套 高亞軍 Video 1 Vivado Design Flow Overview -Video-41 TCL-Vivado-One-World-7

Lauren

GaoVivadoDesignFlow

OverviewThedifferenceofFPGAdesignflowbetweenISEand

VivadoVivadouse

modesDemonstrateprojectmodedesignflow

featuresAgendaISEToolsFPGADesignFlow

OverviewEDKPlatform

StudioSystem

GeneratorCore

Generator.xmp.sgp.xcoUCF

Constraints3rdParty

EDIF.ucf.edn.ngc.ngd.ncd/.pcf.ncd/.ngm/.pcfTRCEMAPPARNGDBuildXSTSpecification Verilog/VHDL.twrBitGen.bit.v/.vhdEachsteprequiresadifferentdata

modelBehavioral

SimulationTiming

SimulationVivado

IDEFPGADesignFlow

OverviewSpecificationVerilog/VHDLSystem

Verilog3rdParty

EDIFXDC

ConstraintsVivadoSystem

BuilderIP,DSP,

uP.v/.vhd.xdc.ednSaveDesignCheckpointat

eachstage

(.dcp)Commondata

modelthroughoutthe

flowBehavioral

SimulationElaboratesynth_designreport_timing_summaryopt_designpower_opt_designplace_designpower_opt_designphys_opt_designroute_designreport_timing_summaryTiming

Simulationwrite_bitstreamVivadoSystemBuilder–SystemLevelDesign

FlowHigh-LevelSynthesis(Vivado

HLS)DSPDesign(System

Generator)IPIntegration(Embedded,

Logic,DSP…)IP

PackagingIP

CatalogXilinx

IP3rdIPUser

IPRTLSystem-Level

IntegrationSynthesisImplementationProgrammingand

DebugDesign

AnalysisConstraintsSimulationDebuggingCross

ProbingRTLEDIFXDCCustomer

IPCC++System

CIP-CentricEverythingneededtosaveandrestorethecurrent

designLogicalNetlist

(EDIF)Constraints

(XDC)PhysicalData(XDEF)Checkpoint

usesDesignprogressDesignanalysisDesign

explorationWhatisaDesign

Checkpoint?synth.dcprouted.dcpplaced.dcpopt.dcpopt_designplace_designroute_designwrite_checkpointwrite_checkpointwrite_checkpointwrite_checkpointDesignCheckpoint:Synthesis:top.dcpOpt:top_opt.dcpPlace:top_placed.dcpRoute:top_routed.dcpTclcommands:write_checkpointread_checkpointProcessesaccesstheunderlyingdatabaseofyour

designEachprocessoperatesonanetlistandwillmodifythenetlistorcreate

anew

netlistDifferentnetlistsareusedthroughoutthedesign

processElaboratedSynthesizedImplementedDesign

DatabaseSynthesisNetlist

OptimizationPower

OptimizationPlacerPhysical

OptimizationRouterVivado

IDEDatabaseExpressiveofdatabase:DesignCheckpointsineachstage

(.dcp)VivadoDesignEntryandUse

Modelproject_name.runsproject_name.srcsproject_name.datasrcednipVivadoxdcsysgensimProject

Modeproject_name.xpr.dcp.rptNon-Project

ModeGUITclTclAllprojectdataisstoredinaproject_namedirectory

containingthe

followingproject_name.xprfile:Objectthatisselectedtoopenaproject(VivadoIDEproject

file)project_name.runsdirectory:Containsallrun

dataproject_name.srcsdirectory:ContainsallimportedlocalHDLsource

files,netlists,andXDC

filesproject_name.datadirectory:Storesfloorplanandnetlist

dataProject

DataProjectmode

advantagesSourcefilemanagementAutomaticdesignprocessanddata

managementIntegratedIPdesign

solutionConfigureandmanagemultiplerunswithvarying

strategiesCross-probingto

RTLConsolidatedmessagingandtrackingofdesign

stateInteractivedesignanalysisandconstraints

assignmentFullTcl

supportUsingtheProjectMode

FlowNon-Projectmode

advantagesPowerfulandflexibleTclbased

environmentStraight-forwardcompilationstyle

flowCommondatamodel–allprocessingdonein

memorySavedesigncheckpointsat

willPowerfulTclAPI–designandtoolconfiguration,robust

reportingUsetheintegrateddesignenvironmentGUIas

neededDesignanalysis,constraintsassignment,implementation

resultsI/Oplannning,floorplanning,debugcore

insertionPerformimplementation

changesUsingtheNon-ProjectMode

FlowDemo:ProjectModeDesign

FlowIP-Centricsystemleveldesign

integrationCreateandpackageIPandaddittoIP

catalogCreateIPsubsystemswithIP

IntegratorEmbeddedprocessor,DSP,

HLSSystemdesignentrythroughhardwarevalidation

flowsAdvanceddesign,analysisandprocessmanagement

capabilitiesFlexibleuse

modelsTclaccessiblecommondatamodelthroughoutthe

flowProjectandcompilationstyle

flowsSupportforthirdpartysoftware

toolsSummaryUg888:designflows

overviewMore

InfoLauren

GaoDesigningwith

IPVivadoIPOverviewVivadoIPDesignFlowNewTool:IP

PackagerDemo:ProjectBasedIPDesign

FlowManageIPDesign

FlowCreateandPackage

IPAgendaVivadoDesignSuiteIPvsISECOREGenerator

IPIPin

ISEIPin

Vivado.xco.xci.ngc.dcp.ucf.xdcXilinxCoreLibItsownsim

source.dcpisnotonlythenetlistbutalso

constraintsIPOutputProductsin

VivadoIPInstantiation

TemplateSynthesized

CheckpointBehavioral

Simulation.veo.vho.dcp.v.vhdl<ip_name>_funcsim.v<ip_name>_funcsim.vhdl<ip_name>_stub.v<ip_name>.vhoFor3rdSimulation

ToolFor3rdSynthesis

ToolExample

DesignTestbenchFlexibleIPUseModelsI

VivadoCurrentProject.dcporCreatestandalonereusableIP

locationsProjectbasedIPmanagementSynthesizeOOCor

globallyLockIPtoaspecificversionorupdatetocurrent

versionProject

Mode Non-Project

Mode.xciread_ipadd_filesimport_ipCreateStandaloneReusableIP

LocationsAddorCreateDesign

SourcesAdd.dcptothe

projectAddExisting

IPAdd.xcitothe

projectHowto

addIPtotheprojectefficiently?EachIPhasitsown

directoryTclProjectBasedIP

Management.dcpRTLGLOBALOOCHowtoDealwithGenerated

XDCIndefault,generatedxdcisusedin

both

Synthesisand

Implementation.Wedonotneedtodoanythingfor

it.report_compile_order

-constraintsOpenIPExample

Designopen_example_project[get_ips

char_fifo]UsingXilinxIPwith3rdPartySynthesis

ToolsUseManageIPflowtocreate

andcustomize

IPGeneratea.dcpforeachIPAddVerilogstubor

VHDLcomponenttoSynplifyPro

projectGenerateanetlistwithSynplify

ProBringthenetlistandall.dcpto

VivadoprojectImplementthedesignwith

Vivado.xci.dcp<ip_name>_stub.v<ip_name>.vho.edfWhenusingXilinxIPtheonlysupportedsynthesistoolisthe

Vivadosynthesis

toolIPVersion

Controlreport_ip_status-name

ip_status_1report_property[get_ips

char_fifo]SomeTclCommandsabout

IPGetalistofIPsinthecurrent

designget_ipsGeneratetargetdataforthespecified

sourcegenerate_targetOpentheexampleprojectfortheindicated

IPopen_example_projectResettargetdataforthespecified

sourcereset_targetUpgradeaconfigurableIPtoalater

versionupgrade_ipMoreinfo:

ug835IP-CentricDesign

FlowIP

PackagerXilinxIP3rdPartyIPUser

IPUserDesignSource(C,RTL,IP,

etc)SimulationmodelsDocExampleDesignTestbenchCustomerRTL

CodeIP

CatalogProjectBasedIPDesign

FlowManageIPDesignFlowCreateandPackage

IPDemoLauren

GaoLogicSimulationwithXSimSimulation

FlowRTL

DesignSynthesizeImplementDebugthe

DesignBehavioral

SimulationVerifyDesignBehavesas

IntendedPostSynthesis

SimulationVerifythesynthesizeddesignmeetsthefunctionalrequirementsandbehavesasexpectedPostImplementation

SimulationClosestemulationto

HWVivadoSupported

SimulatorsVivadoVivado

SimulatorQuestaSimModelSimIESVCSActive-HDLRivierea-PROSimulationlibrariesareprecompiledintheVivado?DesignSuiteforusewiththeVivadosimulator.Youmustcompilelibrarieswhenusingthirdpartysimulatorsxsim.ini<Vivado_Install_Dir>/data/xsim--DefaultlibmappingforSimulatorstd=$RDI_DATADIR/vhdl/xsim/stdieee=$RDI_DATADIR/vhdl/xsim/ieeevl=$RDI_DATADIR/vhdl/xsim/vlsynopsys=$RDI_DATADIR/vhdl/xsim/synopsysunisim=$RDI_DATADIR/vhdl/xsim/unisimunimacro=$RDI_DATADIR/vhdl/xsim/unimacrounifast=$RDI_DATADIR/vhdl/xsim/unifastxilinxcorelib=$RDI_DATADIR/vhdl/xsim/xilinxcorelibsimprims_ver=$RDI_DATADIR/verilog/xsim/simprims_verunisims_ver=$RDI_DATADIR/verilog/xsim/unisims_verunimacro_ver=$RDI_DATADIR/verilog/xsim/unimacro_verunifast_ver=$RDI_DATADIR/verilog/xsim/unifast_verxilinxcorelib_ver=$RDI_DATADIR/verilog/xsim/xilinxcorelib_versecureip=$RDI_DATADIR/verilog/xsim/secureiXSimAddbreakpointinthesource

codegroupdividerAnalogformVCD

dumpingSingleorMultipleSimulation

SetsSubmodule

testbenchTopmodule

testbenchSingleSimulation

SetMultipleSimulation

Setstestbenchfsm_tbsim_1 sim_2MultipleSimulation

SetsUsingdifferentsimulation

settingsSimulationsub

modulesScope&

Objectstop_tbdutABCC1Each

modulecanbeascopecurrent_scopeget_scopesreport_scopesget_objectsreport_objectsScopeVerilog:module,function,task,process,orbegin-end

blocksVHDL:entity/architecturedefinitions,block,function,procedure,andprocessblocksObjectsHDLsignals,variables,orconstantsLauren

GaoLogicSimulationwith

ModelSimcompile_simlib-directoryDirectorypathforsavingthecompiled

results-familyvirtex7,kintex7,kintex7l,artix7,artix7l,zynq,default:

all-languagevhdl,verilog,default:all-libraryUnisim,simprim,xilinxcorelib,edk,default:

all-simulatormodelsim,questa,ies,vcs_mx,riviera,

active_hdl-simulator_exec_pathModelSim:E:\modeltech64_10.2\win64-32bitPerformsimulatorcompilationin32-bitmodeinsteadofthedefault64-bitcompilationCompileXilinxSimulation

LibraryUseModelSimas3rdParty

SimulatorWherecanrun

itInVivadoTcl

consoleInVivadoTcl

shellWhentorun

itAnytimeanewsimulatorversionis

installedAnytimeanewversionofVivadoIDEis

installedHowtorun

itSinglecommandstepby

stepAsTclfile,usesourcecommandsettarget_dir

{E:\Xilinx\Xlib}setsim_exe_path

{E:\modeltech64_10.2\win64}compile_simlib-directory$target_dir-familyall-languageall

\-library

all-simulatormodelsim-simulator_exec_path

$sim_exe_pathCompilation

SummaryShouldWeCompileSimulationLibrary

forDifferent

Project?NOWhy?Setcompiledlibraryasglobal

libraryLauren

GaoSynthesisBasicSynthesis

SettingsSomeSynthesisAttributesCommonlyUsedintheDesignCreateMultiple

RunsAgendaBasicSynthesis

SettingsSomeSynthesisAttributesCommonlyUsedintheDesignCreateMultiple

RunsAgendaSynthesisSettings–Project

Mode.xdcusedinsynthesisSynthesis

strategyTclrunningbefore

synthesisTclrunningafter

synthesislaunch_runs

synth_1SynthesisSettings–Non-Project

Modesynth_design[-namearg][-partarg][-constrsetarg][-toparg][-include_dirsargs][-genericargs][-verilog_define

args][-flatten_hierarchyarg][-gated_clock_conversion

arg][-directivearg][-rtl][-bufgarg][-no_lc][-fanout_limitarg][-shreg_min_sizearg][-modearg][-fsm_extraction

arg][-keep_equivalent_registers][-resource_sharingarg][-control_set_opt_thresholdarg][-quiet]

[-verbose]synth_design-toptop-partxc7k70tfbg676-2-flatten_hierarchy

none-mode:default,out_of_context

(OOC)synth_design-toptop-partxc7k70tfbg676-2–mode

out_of_contextInISEUncheck“AddI/OBuffers”

(-iobuf)InVivadoSetthemoduleasoutofcontext

moduleSettingaBottom-Up

FlowUsingtheOut-of-Context

FlowThenhavetheirown.dcp

files-flatten_hierarchy

optionsnoneThisoptioninstructsthesynthesistooltoneverflattenthe

hierarchyTheoutputofsynthesiswillhavetheexactsamehierarchyastheoriginal

RTLfullThisoptioninstructsthetooltofullyflattenthehierarchyleavingonlythetop

levelRebuiltThisisthedefaultflatten_hierarchy

optionRebuiltallowsthesynthesistooltoflattenthehierarchy,performsynthesis,andthenrebuildthehierarchybasedontheoriginal

RTLThisvalueallowstheQoRbenefitofcross-boundaryoptimizations,withafinalhierarchythatissimilartotheRTLforeaseof

analysisProjectmode:thisoptioncanbesetusingtheSynthesisSettingsbuttonNon-project

mode:-flatten_hierarchysynth_design-topbft-partxc7k70tfbg484-2-flatten_hierarchy

noneWhatisLUT

Combining?-no_lcb1<=(a1anda2)ora3or(a4xor

a5);b2<=(a1anda2anda3)or(not(a4xor

a5));O6LUTO5O6LUTO5O6LUTO5-no_lc

unchecked(EnableLUT

Combing)-no_lcchecked(DIsableLUT

Combing)b1&b2

sharecommon

inputs1

LUT2

LUTResourceUtilizationLUTcombiningleveragesthedual-outputLUT

(O5/O6)Pro:saves

areaCon:couldinduce

congestionToolsbehaviorXST/Synplifycombineby

defaultVivadodisableLUTcombingbydefaultinsynthesissettingsUsereport_utilization

andlookforLUTswithO5andO6afterimplementationGuideline: If>15%ofLUTusebothO5andO6,

then–ConsiderturningoffLUTcombiningin

synthesis-no_lcSliceLogic

Distribution+++|Site

Type | Used|+++|Slice|LUTas

Logic| usingO5output

only| usingO6output

only| usingO5and

O6|||||45910|120084|422|105082|14580|BasicSynthesis

SettingsSomeSynthesisAttributesCommonlyUsedintheDesignCreateMultiple

RunsAgendaShiftRegisterCodingExamplewith

srl_styleVHDLVerilog7-series:SRL16ESRLC32EBasic

Ports:Q,D,CLK,CE,ADonot

supportreset1to32clockcycleshiftregisterimplementedwithinasinglelook-uptable

(LUT)srl_style

ValuesSRLSRLFFFFSRLFFFFFFFFFFSRLcontrolsshiftregister

decomposition1234FF 5srl_regreg_srlreg_srl_regregistersrlDonotsupportRESETwith

SRLMakesure–shreg_min_sizeis

reasonableIf–shreg_min_sizeis8,shiftregisterdepthis4,srl_styleissrl_reg,thesynthesisresultisnotSRL+FFbutcascading

FFsSupportfordynamicSRL

inferenceAdvantagesof

SRLless

areaUsingasingleSRLyoucanimplementupto32-cycleshift

registerPerformanceRoutingdelaysbetweencascadedffsdecreasestheperformance(Fmax)comparingtoSRLTipsTheclock-to-outputtimeofaflopismuchlowerthanclock-to-outputofanSRLThat'swhyitmakessensetoaddaflopontheoutputofan

SRLWhenandHowtoUse

srl_style?SRLFFSRLFFLess

areaHigh

Performanceram_style&

rom_styleInstructstheVivadosynthesistoolonhowtoinfermemoryAcceptedvaluesaccepted

areblock:InstructsthetooltoinferRAMBtype

componentsdistributed:InstructsthetooltoinfertheLUT

RAMsPlacethisattributeonthearraythatisdeclaredforthe

RAMVerilog:(*ram_style="distributed"*)reg[data_size-1:0]

myram[2**addr_size-1:0];VHDL:attributeram_style:

string;attributeram_styleofmyram:signalis"distributed

";InstructsthesynthesistoolhowtodealwithsynthesisarithmeticstructuresWhicharithmetictypestructuresgointoDSP48blocksby

defaultMultMult-add&

mult-subMult-accumulateAdders,subtracters,andaccumulatorsareimplementedwiththefabricinsteadofwithDSP48blocksbydefaultCantheygointo

DSP48?YES,applyuse_dsp48to

themAccepted

values“yes”and“no”use_dsp48+FF24-bit24-bitblack_boxItcanturnawholelevelofhierarchyoffandenablesynthesistocreateablackboxforthatmoduleor

entityThelegalvaluesare“yes”and

“no”Thisattributecanbeplacedonamodule,entity,or

componentdont_touchUsetheDONT_TOUCHattributeinplaceof

KEEPUnlikeKEEP,DONT_TOUCHisforward-annotatedtoplaceandrouteto

preventlogic

optimizationThelegalvaluesare“true”and

“false”Thisattributecanbeplacedonanysignal,module,entity,or

componentfsm_encondingItcontrolshowastatemachineis

encodedThelegalvalues"one_hot","sequential","johnson","gray",and

"auto“Itcanbeplacedonthestatemachine

registersSomeOther

AttributesExamples

1black_boxVerilog(*black_box*)moduletest(in1,in2,clk,

out1);VHDLattributeblack_box:

string;attributeblack_boxofbeh:architectureis"yes";dont_touchVerilog(*dont_touch="true"*)wire

sig1;assignsig1=in1&in2;assignout1=sig1&

in2;VHDLsignalsig1:std_logicattributedont_touch:

string;attributedont_touchofsig1:signalis

"true";Example

2Verilog(*fsm_encoding="one_hot"*)reg[7:0]

my_state;VHDLtypecount_stateis(zero,one,two,three,four,five,six,seven);signalmy_state:count_state;attributefsm_encoding:string;attributefsm_encodingofmy_state:signalis

"sequential";fsm_encodingBasicSynthesis

SettingsSomeSynthesisAttributesCommonlyUsedintheDesignCreateMultiple

RunsAgendaCreateNew

RunsFlow→

CreateRunsDesignRuns→

CreateRunsRuns

type:SynthesisImplementationBothCreateandManageMultiple

Runssynth_1impl_1impl_2impl_3synth_1impl_1synth_2impl_2synth_1impl_1synth_2Design

Runimpl_4Eachruncanhavedifferentconstraint,differentpartanddifferentstrategyImplrunisbasedonsynthrunwhichisimplrun’sparent

runOnlyonerunisactive.current_run[get_runs

synth_1]Runresultiscalleddesign.

current_designRuncanalsobedeleted.delete_run

synth_2Message

ManagementFilterdifferent

typesGroup

infoDiscardold

messageSupportbothtop-downandbottom-upsynthesis

flowSupportmultiplerunsforexperimentsPowerfulmessages

managementSummaryLauren

GaoVivado

ImplementationNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaVivadoImplementation

Sub-processesopt_designpower_opt_designplace_designphys_opt_designroute_designwrite_bitstreamLogicOptimization(Optional)Power

OptimizationPlacement(Optional)Physical

SynthesisRoutingGeneratea

BitstreamNewFeature:

DirectivedirectivedirectiveCommandoptionto“direct”behaviortowrdalternate

goalDifferent

algorithmsDifferentobjectivesImplementationcommandswith

–directiveopt_design,place_design,

phys_opt_design,route_designAlternativeflowsto

useWhenthedefaultflowdoesnotmeetdesign

goalsWhentoolruntimeincreasecanbe

accommodatedUsesdifferent

algorithmsNotrandomseedslikeISEcost

tablesMoreconsistentandpredictable

behaviorHelp-opt_designtofindallthe

directives-directive

ExploreAllcommandshave–directive

ExploreISE

MAPISE

P&RISE

–effort_levelVivado

-directive-effort_levelhigh-directive

Explore-effort_levelhigh

-area_mode-directiveExploreArea(opt_design

only)-directive:Replacementfor

–effort_levelAutomaticmappingforallimplementation

commandsISE–effort_levelVivado-directive-effort_levelhigh-effort_level

medium-effort_levellow-effort_levelquick-directive

Explore-directive

Default-directiveRumtimeOptimized-directive

QuickNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaImplementation

StrategyDifferentdirectivesTools→options→StrategiesStrategiesaregroupedby

category–Performance,Area,Power,Flow,

CongestionStrategies

ExampleDesignflowPerformance_ExploreArea_ExplorePower_DefaultOptFlow_RunPhysOptCongestion_SpreadLogic_highopt_design√√√√√-directiveExploreExploreAreaDefaultDefaultDefaultpower_opt_design××√××place_design√√√√√-directiveExploreDefaultDefaultDefaultSpreadLogic_highpower_opt_design(post-place)×××××phys_opt_design√×√√√-directiveExploreDefaultExploreAggressiveFanoutOptroute_design√√√√MoreGlobalIterations-directiveExploreDefaultDefaultDefaultDirectives->commandlevel

behaviorStrategies->implementationrun-levelbehavior,acombinationofdirectivesDifferentstrategymay

haveDifferent

directivesVivadoimplementationdefault:-directiveareall

defaultPerformance_Explore:-directiveareall

ExploreDifferentdesign

flowsVivadoimplementationdefault:opt_design,place_design,

route_designPerformance_Explore:opt_design,place_design,phys_opt_design,

route_designEachstrategyhasdifferentdirectivesfortheimplcommandstepsYoucancustomizeyourown

strategyUserdefined

strategiesThePerformance_Explorestrategyisagoodfirstchoice,becauseitcoversalltypesofdesignsThePerformancestrategiesaimtoimprovedesignperformanceatthe

expenseof

runtimeStrategiescontainingthetermsSLLorSLRareforusewithSSIdevicesonlyImplementation

StrategyTcl

APITcl

APITcl

APIAllimplementationsub-processeshaveTcl

APItcl.pre:commandsshouldbeexecutedbeforethis

processtcl.post:commandsshouldbeexecutedafterthis

processExampleopt_design.tclNewFeature:

DirectiveImplementation

StrategyRunImplementationinProject-ModeandNon-Project

ModeAgendaInProjectMode,theVivadoIDEallowsyou

toDefinemultipleimplementation

runsRunmultiplestrategiesonasingle

designCustomizeimplementationstrategiestomeetspecificdesign

requirementsSavecustomizedimplementationstrategiestouseinother

designsNon-ProjectModedoesnotsupportpredefinedimplementationrunsand

strategiesRunImplementationinProjectModewith

GUIlaunch_runs[-jobsarg][-scripts_only][-all_placement][-dirarg][-to_steparg][-next_step]

[-hostargs][-remote_cmd

arg][-email_toargs][-email_all][-pre_launch_script

arg][-post_launch_scriptarg][-force][-quiet][-verbose]runs...to_stepopt_design,power_opt_design,place_design,

power_opt_design(post_place)Phys_opt_design,route_design,

write_bitstream-to_step

place_design-to_step"power_opt_design

(Post-Place)"RunImplementationinProjectModewith

Tcllaunch_runsimpl_1launch_runsimpl_2-to_step

place_designcd

{F:\Vivado\Tutorial\logic_sim\XSim_Tutorial.runs\impl_2}open_checkpointsinegen_demo_placed.dcplaunch_runsimpl_2

-next_stepRunImplementationinNon-Project

ModeNon-projectbaseddesignsmustbemanuallymovedthrougheachstepoftheimplementationprocessusingTcl

commandsplace_design[-directivearg][-no_timing_driven][-unplace][-cellsargs][-post_place_opt][-quiet]

[-verbose]-post_place_optPotentiallyimprovecriticalpathtimingattheexpenseofadditional

runtimeThisoptimizationcanberunatanystageafterplacement,andcanbe

particularlyeffectiveonarouted

designTheoptimizationexaminestheworstcasetimingpathsandtriestoimproveplacementtoreduce

delayTheoptimizationisperformedonafullyplaceddesignwithtiming

violationsThe-directiveoptioncontrolstheoverallplacementstrategy,andisnotcompatiblewithanyspecificplace_design

options.place_designplace_designphys_opt_designroute_designplace_design-post_place_optroute_designroute_design[-unroute][-re_entrantarg][-netsargs][-physical_nets][-pinarg][-directivearg][-no_timing_driven][-preserve]

[-delay][-free_resource_mode]-max_delayarg-min_delayarg[-quiet]

[-verbose]-preservePreserveexisting

routing-delayUsewith-netsor-pinoptiontorouteindelaydriven

mode-max_delayUsewith-pinoptiontospecifythemax_delayconstraintonthe

pin-min_delayUsewith-pinoptiontospecifythemax_delayconstraintonthe

pinroute_designroute_design-delay-nets$myCriticalNetsroute_design-preserve-directiveRuntimeOptimizedroute_design-unroutephys_opt_design[-fanout_opt][-placement_opt]

[-rewire][-critical_cell_opt][-dsp_register_opt]

[-bram_register_opt][-bram_enable_opt][-shift_register_opt][-hold_fix]

[-retime][-force_replication_on_netsargs][-directivearg]

[-critical_pin_opt][-quiet]

[-verbose]Commandoptionslimittheoptimizationscopetoonlythespecifiedoptions–Oneoptionper

optimizationphys_opt_designTiming-drivenoptimizationsincludedby

defaultFanout:replicatedriversofhighfanout

netsPlacement:move

cellsRewiring:restructurelogic

conesCriticalcells:replicatecriticalpath

cellsDSPregisters:moveregistersto/from

DSPBRAMregisters:moveregistersto/from

BRAMShiftregisters:moveregistersfrom

SRLsCriticalpins:swapphysicalLUTinput

pinsVeryhighfanout:replicatedriversofvery-highfanout

netsBRAMenable:improvepower-optimizedBRAM

enablesPage

20WhatOptimizationsare

Performed?Optional

optimizationsForcednetreplication:replicateregardlessoftiming

slackRegisterretiming:balanceregistersacrosscombinational

delaysHold-fix:insertdatapath

delayPage

21WhatOptimizationsare

Performed?Differentstrategymayhavedifferentdesignflowswith

differentdirectivesDirectiveisincompatiblewithotheroptionsinopt_design,place_design,phys_opt_designand

route_designDirectivesandstrategiesprovidealternateflowstotrywhenthe

tooldefaultsdon’tmeettimingondifficult

designsSomeTclcommandcanhelptomeet

timingplace_design

–post_place_optphys_opt_designroute_design–delay

–netsPerformance_Exploreishelpfulfortiming

closureSummaryLauren

GaoIncremental

ImplementationBasicIncrementalCompile

FlowRunningIncrementalCompileinProjectModeandNon-ProjectModeAdvancedAnalysisforIncremental

CompileDemoAgendaIncrementalCompile

FlowRTL

ChangeNetlist

ChangeRevisedRTLSynthesisRevisedNetlistIncrementalPlace&