通信與電子設(shè)計(jì)實(shí)驗(yàn)硬件連接關(guān)系

33脈沖觸發(fā)開關(guān)(4位64M0/1控制開關(guān)(8位4個(gè)Xilinx Xilinx視頻擴(kuò)展分AlteraCPLDNorFLASH外擴(kuò)單片擴(kuò)展子U50：CPLD型號(hào)：XC95144XL-10TQ144：familyXC95144XLDeviceXC95144XLSpeed-10Package U46：FPGA型號(hào)：XC2V2000：familyVirtex2,deviceXC2V2000。Speed-4。Package U1：ARM型號(hào)：三星S3C2410,最高工作時(shí)鐘200MHzU30：ALTERACPLD型號(hào)：EPM7032TC44-10U42：ALTERACPLD型號(hào)：EPM7032TC44-10U33：ALTERACPLD型號(hào)：EPM7032TC44-10 CPLD1234567899567234輸出數(shù)碼管（動(dòng)態(tài)掃描模式:共陰極a8個(gè)數(shù)碼管的共用正極控bcdefg8個(gè)數(shù)碼管的共陰極控制0/1控制開關(guān)（ON接到地，OFF接到KEY1KEY3無(wú)無(wú)KEY2KEY4無(wú)無(wú) FPGA控制所有CPLD12345678938個(gè)DIP開關(guān)的通斷狀態(tài)通過FPGA_DipSwitch_en和FPGA_DipSwitch_n[3..0]輸入到FPGA，其中FPGA_DipSwitch_en為串行數(shù)據(jù)傳遞使能信號(hào)，當(dāng)其為高電平(或上升沿)時(shí)，F(xiàn)PGA_DipSwitch_n[3..0]數(shù)據(jù)有效。000~111的狀態(tài)，0表示ON，1表示OFF。4，32LEDFPGAFPGA_LED_dFPGA_LED_bits[4..0]完成。00000~1，F(xiàn)PGA_LED_d（高電平）還是滅（低電平FPGA_Seg7_HEX[3..0]FPGA_Seg7_en_n用來(lái)指示數(shù)據(jù)傳遞，即當(dāng)其為低電平時(shí)，F(xiàn)PGA_Seg7_bits[2..0]三、FPGAXC2V2000FPGAS11開關(guān)控制四個(gè)全局時(shí)鐘引腳的時(shí)鐘連（OFF/ONOFFON時(shí)提供48MHz的時(shí)鐘。FPGA式000主串（與模式引腳一起認(rèn)IO111配置期間是否上011主接高電平時(shí),110從IO101時(shí)，相應(yīng)的控制為高電平;ON時(shí)相應(yīng)的控制為低電平。U55 V2000TDOV8000V2000_TDIU55V2000V8000U47U55V2000沒焊時(shí) 123456789DS38a8個(gè)bcdefgAD/AD板接信名123456789地地地地地地地ADJADJ 方向ED[0-31]16245U42CPLDDC_EMIFA_OE# U35 UARTU41UARTU41 23568’TCE1=’0’TCE2=’0’TCE3=’0’時(shí)為’0’,TCE1=’0’DC_AOE=’0’且 DSPU40SST39VF040- NorU42U41 U42U42AJ109BU34,U35 A[0..11]LEDLEDLED PCIPCI無(wú)啟動(dòng)模式（默認(rèn)PCIPROM無(wú)效（默認(rèn)PCIROMBITEMIF8NoNoNoCPU時(shí)鐘NoCPU時(shí)鐘0040015021106131184、DSPCLKIN11101201600十、DSPARMHD00~HD15DSP端HPI控制引腳的譯碼是通過U33EPM7032CPLD實(shí)現(xiàn)的，如上圖所示。U33將來(lái)自ARM的片選信號(hào)nGCS3,nGCS5ADDR[0..4]（Laddr[0..4]162245緩沖器）DSPHPI相應(yīng)的控制信號(hào)?？刂七壿?VHDL代碼)如下：HCNTRL0<=ADDR1whennGCS3='0'else whennGCS3='1'; whennGCS3='1'; whennGCS3='0'else whennGCS3='1'; whennGCS3='0'else whennGCS3='1'; <=(nWEandnOE)whennGCS3='0'else whennGCS3='1';HDS2 十一、ARMLCD顯示模塊用的是SHARPLQ035Q7DH01TFT觸摸屏模塊，其引腳定義見下表，其它內(nèi)容請(qǐng)參考Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-5、USB6、8、ARMLIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all; Vcom Samplingstart framesynLCD_LP linesyn ClocksignalofGate DataENDARCHITECTUREBehaviorOFLCD_CONSIGNAL SIGNALcounter_for_mod SIGNALcounter_for_point:std_logic_vector(8downto0); SIGNALs_lcd_cls SIGNALcounter_for_line: SIGNALline_den Interal_dclk<=notLCD_DCLK <=not CASEcounter_for_modWHEN =>WHENOTHERS=>counter_for_mod<=counter_for_mod+"001";ENDEND (VLINE='1')elsif(Interal_dclk'EVENTANDInteral_dclk='0')thenend (counter_for_point="000000110"andline_den='1')then

end

if(Interal_dclk'eventandInteral_dclk='1')thenif(counter_for_point="011111111")thens_lcd_rev<=notendif;endendif(VFRAM='1')thenelsif(s_lcd_cls'eventands_lcd_cls='0')endif;if(counter_for_line>="000000110"andcounter_for_line<="101000101")thenendif;endprocess;if(line_den='1')thenendif; <=nGCS0ANDnGCS1ANDnGCS2ANDnGCS3ANDnGCS4ANDnGCS5ANDnFWEANDtem_buffe