基于MT9M033設計的FPGA HD IP監(jiān)視攝像機方案

基于MT9M033設計的FPGAHDIP監(jiān)視攝像機方案ThisuniquesolutionfeaturesAltera＇slow－costCyclone?IIIorCycloneIVFPGAsandintellectualpropertyfromEyelyticsandApicalsupportingAltaSens＇1080p60A3372E3－4TandAptina＇s720p60MT9M033HDWideDynamicRange(WDR)CMOSimagesensors.Theall－in－onesolutionofferssurveillanceequipmentmanufacturerstheabilitytoreduceboardspace,lowerpowerconsumption,increaseflexibilityandreducedevelopmenttimecomparedtopreviousarchitecturesusingtraditionaldigitalsignalprocessorsandASSPs.TraditionaldigitalsignalprocessorsandASSPsdon＇thavetheprocessingpowerrequiredtoacceptthelargebandwidthofdatafrom1080pand720pWDRCMOSsensors(forinstance,afullHDrasteris2200x1125pixelsx16+bitsperpixelx60framespersecond,resultingin>2Gbpsbandwidth).Altera＇sCycloneseriesFPGAsdeliverthebandwidthandprocessingperformanceneeded,handlinglargeamountsofdatageneratedbytoday＇sHDWDRCMOSimagesensors.Inpreviousdesigns,HDWDRcamerasystemsrequiredFPGAstoperformthe“frontend”dataprocessingwhileadigitalsignalprocessororanASSPhandledthe“backend”videoencoding.Now,allofthesechipscanbereplacedbyasingleAltera?FPGA.ThefunctionsofAltera＇sHDsurveillanceIPcamerareferencedesigninclude：Apical＇sISPincorporatingbest－in－classWDRprocessing“iridix”togetherwithadvancedtemporalandspatialnoisereductionApical＇s“checkerboarddemosaic”corefortheAltasensA3372E3－4TWDRmode“3A”functions,suchasautoexposureandautowhitebalanceimplementedinsoftwareonAltera＇sNios?IIembeddedsoftcoreprocessorEyelytics＇H.264videoencoder,capableof720－lineprogressive30frames－per－secondencodingor1080－lineprogressive15frames－per－secondencodinginmainprofileAltera＇striple－speedEthernetMACintellectualpropertycore圖1。參考設計外形圖一．Next－Generation,MegapixelWDRImageSensorMT9M033Best－In－Class,HDVideoSensorProviding720pat60fpsHDstreaming,thisimagesensoroffershigh－speedvideoperformance.Superior,Low－LightPerformanceDynamicpixelresponsetechnologysignificantlyimprovessensitivityforsuperblow－lightperformance.ExceptionalImageQualityTheMT9M033hasadynamicrangeofupto120dB,producingcrystal－clearimagesinalllightingconditions.PerfectforDay／NightCameraApplicationsHighquantumefficiencyinvisible／NIRrangeimprovesversatilityforuseindayandnightapplications.All－PurposeImageSolutionTheperfectchoiceformainstreamsurveillancelensformats.MT9M033主要特性：?Best－in－class,low－lightperformance?HDvideo(60fps@720p)?Linearorhighdynamicrangevideostreaming?Videoandsnapshotmodes?2X2binningandwindowing?Flexiblerow－skipmodes?Parallelandserialouputs?On－chipAEandstatisticsengine?SupportforexternalLEDorflash?Autoblacklevelcalibration?Contextswitching?Sophisticatedcamerafunctions,includingautoexposurecontrol,windowing,binning,andhigh－speedrow－skippingmode?Programmablethroughtwo－wireserialinterface?AdvancegaincontrolMT9M033技術指標：?ImagingArray?OpticalFormat：1／3－inch?ActiveArray：1280(H)x960(V)?ImagingArea：3.54mm(H)x2.69mm(V)Speed／Output?FrameRate：60fps@720p(HDmode);45fps@fullresolution?DataRate：27Mb／s?MasterClock：74.25MHz?DataFormat：Serial(HiSPi),parallel(12－or14－bit)Sensitivity?PixelSize：3.75μmx3.75μm?PixelDynamicRange：120dB?Responsivity：6.0V／lux－secPower?Supply：I／O：1.8VCore：1.8VAnalog：2.8V?Consumption：~300mWTemperatureRange?Operating：–20°Cto+70°C?Storage：–40°Cto+125°CPackage：iLCCordieMT9M033應用：?Surveillancecameras?Automaticlicenseplaterecognition(ALPR)cameras?Widedynamicrange(WDR)cameras?HDTV?Day／Nightcameras?Domecameras?Pan,tilt,zoomcameras圖2。MT9M033方框圖二．Cyclone?III開發(fā)板TheCyclone?IIIdevelopmentboardprovidesahardwareplatformfordevelopingandprototypinglow－power,high－volume,feature－richdesignsaswellastodemonstratetheCycloneIIIdevice＇son－chipmemory,embeddedmultipliers,andtheNios?IIembeddedsoftprocessor.Withupto4－Mbitsofembeddedmemoryand288embedded18－bitx18－bitmultipliers,theCycloneIIIdevicesuppliesanabundanceofinternalmemorywhilealsoprovidingexternalsupportforhigh－speed,low－latencymemoryaccessviadual－channelDDRSDRAMandlow－powerSRAM.BuiltonTSMC＇s65－nmlow－powerprocesstechnology,CycloneIIIdevicesaredesignedtoprovidelowstaticanddynamicpowerconsumption.Additionally,withthesupportoftheQuartus?IIsoftware＇sPowerPlaytechnology,designsareautomaticallyoptimizedforpowerconsumption.Therefore,theCycloneIIIdevelopmentboardprovidesapower－optimized,integratedsolutionformemory－intensive,high－volumeapplications.Accordingly,theCycloneIIIdevelopmentboardisespeciallysuitableforwireless,videoandimageprocessing,andotherhigh－bandwidth,parallelprocessingapplications.ThroughtheuseofAltera?－providedvideoandimageintellectualproperty(orotherMegaCore?functions)andboardexpansionconnectors,youcanenabletheinter－operabilityoftheCycloneIIIdevice,allowingapplication－specificcustomizationofthedevelopmentboard.TheCycloneIIIdevelopmentboardhasthefollowingmainfeatures：■Higherlogicdensitytoimplementmorefunctionsandfeatures■Moreembeddedmemoryforhigh－bandwidthapplications■ExpandablethroughtwoAlteraHighSpeedMezzanineCard(HSMC)connectors■256－MBofdualchannelDDR2SDRAMwitha72－bitdatawidth■Supportshigh－speedexternalmemoryinterfacesincludingdual－channelDDRSDRAMandlow－powerSRAM■Fouruserpush－buttonswitches■EightuserLEDs■PowerconsumptiondisplayTheCycloneIIIdevelopmentboardprovidesthefollowingadvantages：■Uniquecombinationoflow－cost,low－powerCycloneIIIFPGAthatsupportshigh－volume,memory－intensivedesigns■Highestmultiplier－to－logicratioFPGAintheindustry■Lowestcost,density－andpower－optimizedFPGA■QuartusIIdevelopmentsoftware＇spoweroptimizationtoolsTheboardfeaturesthefollowingmajorcomponentblocks：■780－pinAlteraCycloneIIIEP3C120FPGAinaBGApackage●119Klogicelements(LEs)●3,888Kbitsofmemory●28818x18multiplierblocks●Fourphaselockedloops(PLLs)●20globalclocknetworks●531userI／Os●1.2Vcorepower■256－pinAlteraMAX?IIEPM2210GCPLDinaFineLineBallGridArray(FBGA)package●1.8Vcorepower■On－boardmemory●256MBdual－channelDDR2SDRAM●8MBSRAM●64MBflashmemory■FPGAconfigurationcircuitry●MAXIICPLDandflashpassiveserialconfiguration●On－boardUSB－Blaster?circuitryusingtheQuartusIIProgrammer■On－boardclockingcircuitry●TwoclockoscillatorstosupportCycloneIIIdeviceuserlogic?50－MHz?125－MHz●80I／O,6clocks,SMBus,andJTAG●SMAconnectorforexternalclockinputandoutput■Generaluserandconfigurationinterfaces●LEDs／displays：?EightuserLEDs?Onetransmit／receiveLED(TX／RX)perHSMCinterface?OneconfigurationdoneLED?EthernetLEDs?User7－segmentdisplay?Powerconsumptiondisplay●MemoryactivityLEDs：?SRAM?FLASH?DDR2Top?DDR2Bottom●Push－buttons：?Oneuserresetpush－button(CPUreset)?Fourgeneraluserpush－buttons?Onesystemresetpush－button(userconfiguration)?Onefactorypush－buttonswitch(factoryconfiguration)●DIPswitches：?OneMAXcontrolDIPswitch?OneJTAGcontrolswitch?EightuserDIPswitches●Speakerheader■Displays●128x64graphicsLCD●16x2linecharacterLCD■Powersupply●14V－20VDCinput●On－boardpowermeasurementcircuitry●Upto19.8WperHSMCinterface■Mechanical●6”x8”board●Bench－topdesignCycloneIIIEP3C120開發(fā)板圖3。CycloneIIIEP3C120開發(fā)板外形圖圖4。CycloneIIIEP3C120開發(fā)板方框圖圖5。CycloneIIIEP3C120開發(fā)板電路圖（1）圖6。CycloneIIIEP3C120開發(fā)板電路圖（2）圖7。CycloneIIIEP3C120開發(fā)板電路圖（3）圖8。CycloneIIIEP3C120開發(fā)板電路圖（4）圖9。CycloneIIIEP3C120開發(fā)板電路圖（5）圖10。CycloneIIIEP3C120開發(fā)板電路圖（6）圖11。CycloneIIIEP3C120開發(fā)板電路圖（7）圖12。CycloneIIIEP3C120開發(fā)板電路圖（8）圖13。CycloneIIIEP3C120開發(fā)板電路圖（9）圖14。CycloneIIIEP3C120開發(fā)板電路圖（10）圖15。CycloneIIIEP3C120開發(fā)板電路圖（11）圖16。CycloneIIIEP3C120開發(fā)板電路圖（12）圖17。CycloneIIIEP3C120開發(fā)板電路圖（13）圖18。CycloneIIIEP3C120開發(fā)板電路圖（14）圖19。CycloneIIIEP3C120開發(fā)板電路圖（15）圖20。CycloneIIIEP3C120開發(fā)板電路圖（16）圖21。CycloneIIIEP3C120開發(fā)板電路圖（17）圖22。CycloneIIIEP3C120開發(fā)板電路圖（18）三．BitecDVIHSMC接口板Th