組成原理第六章risc cpu設(shè)計實例v1 2014

RISC

CPU

設(shè)計實例一個簡單的RISC總體結(jié)構(gòu)如下圖所示。Load_R0Load_R1Load_R2Load_R3Load_PCInc_PCSel_Bus_1_MuxLoad_IRLoad_Add_RegLoad_Reg_YLoad_Reg_ZZeroSel_Bus_2_MuxRISC_SPMR0R1R2R30

1

2

3

4Mux_1Reg_Y0

1

2Mux_1Add_RBus_1ALUalu_zero_flagReg_ZZflagBus_2writemem_wordRISC_SPM是一個存儲程序的RISC CPU，由三個功能單元構(gòu)成：處理器、控制器和存儲器。指令從存儲器中提取、譯碼和執(zhí)行，完成：對算術(shù)邏輯單元（ALU）中的數(shù)據(jù)進(jìn)行操作；改變寄存器中的內(nèi)容；改變程序計數(shù)器（

PC）、指令寄存器（

IR）和地址寄存器（ADD_R）中的內(nèi)容；改變存儲器中的內(nèi)容；檢索存儲器中的數(shù)據(jù)和指令；控制數(shù)據(jù)在系統(tǒng)總線中的移動。RISC

CPU

設(shè)計實例RISC_SPM：處理器處理器包括寄存器、數(shù)據(jù)通道、控制線，以及能按照保存在指令寄存器中的操作碼對ALU的操作數(shù)進(jìn)行算術(shù)與邏輯操作的ALU。第一個多路復(fù)用器Mux_1決定送往Bus_1的數(shù)據(jù)源；第二個多路復(fù)用器Mux_2決定送往Bus_2的數(shù)據(jù)源。RISC_SPM：ALUALU有兩個操作數(shù)數(shù)據(jù)通道，data_1和data_2，它的指令集僅限于

ADD、SUB、AND和NOT。RISC

CPU

設(shè)計實例RISC_SPM：控制器所有動作的時序都由控制器決定?？刂破鞲鶕?jù)要執(zhí)行的指令把數(shù)據(jù)傳送到目的地。因此，控制器的設(shè)計完全依賴于ALU的技術(shù)指標(biāo)、數(shù)據(jù)通道資源和可利用的時鐘方案?？刂茊卧淖饔茫簺Q定何時裝載寄存器；選擇數(shù)據(jù)通過多路選擇器的數(shù)據(jù)通道；決定何時將數(shù)據(jù)寫入存儲器中；控制該結(jié)構(gòu)中的三態(tài)總線。RISC

CPU

設(shè)計實例RISC_SPM：指令集CPU由機器語言程序控制，該程序是由存儲在存儲器中的指令集組成的。因此，控制器的設(shè)計除了依賴于數(shù)據(jù)通路的結(jié)構(gòu)外，還依賴于處理器的指令集（也就是程序所執(zhí)行的指令）。單字節(jié)指令：NOP、ADD、AND、NOT、SUB兩字節(jié)指令：RD、WR、BR、BRZRISC

CPU

設(shè)計實例RISC_SPM：控制器設(shè)計控制器可以設(shè)計成一個有限狀態(tài)機（FSM）。在給定結(jié)構(gòu)圖、指令集及設(shè)計中所用的定時方式的情況下，還必須指定狀態(tài)機的狀態(tài)。狀態(tài)機有三個操作階段：取指令、譯碼和執(zhí)行。取指令階段是從存儲器中得到指令；譯碼階段是編譯指令、控制數(shù)據(jù)通道和裝載寄存器；執(zhí)行是產(chǎn)生指令的結(jié)果。取指令階段需要兩個時鐘周期，一個時鐘周期用來裝載地址寄存器，另一個時鐘周期用來從存儲器中得到給定地址的數(shù)據(jù)字。譯碼階段在一個時鐘周期內(nèi)完成。執(zhí)行階段可能需要0個、1個或2個以上的時鐘周期，這主要取決于所執(zhí)行的指令。RISC

CPU

設(shè)計實例RISC_SPM：控制器設(shè)計（繼）RISC_SPM控制器共有12個狀態(tài)：S_idle：當(dāng)復(fù)位有效時進(jìn)入的狀態(tài)，不執(zhí)行任何操作；S_fet1：把程序計數(shù)器中的內(nèi)容裝入地址寄存器；S_fet2：將地址寄存器指定地址中的數(shù)據(jù)字裝入指令寄存器；S_dec：對指令寄存器譯碼，產(chǎn)生控制數(shù)據(jù)通道和寄存器傳輸?shù)男盘?；S_ex1：對于單字節(jié)指令，執(zhí)行ALU操作；S_rd1：將RD指令的第二字節(jié)裝入地址寄存器，并增加PC值；S_rd2：用S_rd1中所裝載地址中的數(shù)據(jù)來裝載目的寄存器；S_wr1：將WR指令的第二字節(jié)裝入地址寄存器，并增加PC值；S_wr2：用S_wr1中所裝載地址中的數(shù)據(jù)來裝載目的寄存器；S_br1：將BR指令的第二字節(jié)裝入地址寄存器，并增加PC值；S_br2：用S_br1中所裝載地址中的數(shù)據(jù)來裝載PC；S_halt：捕獲有效指令編碼失敗的默認(rèn)狀態(tài)。RISC

CPU

設(shè)計實例RISC_SPM：控制器設(shè)計（繼）RISC

CPU

設(shè)計實例RISC

CPU

設(shè)計實例S_idle0rstS_fet1/Sel_PCSel_Bus_1Load_Add_R1S_fet2/Sel_MemLoad_IRInc_PC2S_dec3NOPWRSel_PCSel_Bus_1Load_Add_RS_wr1/Sel_MemLoad_Add_RInc_PC7src=R0src=R1src=R2Sel_R0writeS_wr28Sel_R1writeSel_R2writeSel_R3writeRISC

CPU

設(shè)計實例S_idle0rstS_fet1/Sel_PCSel_Bus_1Load_Add_R1S_fet2/Sel_MemLoad_IRInc_PC2S_dec3NOPNOTsrc=R0src=R1src=R2Sel_R0Sel_Bus_1Sel_R1Sel_Bus_1Sel_R2Sel_Bus_1Sel_R3Sel_Bus_1dest=R0dest=R1dest=R2Sel_ALULoad_R0Load_Reg_ZSel_ALULoad_R0Load_Reg_ZSel_ALULoad_R0Load_Reg_ZSel_ALULoad_R0Load_Reg_ZRISC

CPU

設(shè)計實例S_idle0rstS_fet1/Sel_PCSel_Bus_1Load_Add_R1S_fet2/Sel_MemLoad_IR

Inc_PC2S_dec3NOPBRBRZzeroSel_PCSel_Bus_1Load_Add_RS_br210Sel_MemLoad_PCInc_PCS_br1/Sel_MemLoad_Add_R9S_halt11RISC

CPU

設(shè)計實例module

RISC_SPM

(clk,

rst);parameter

word_size

=

8;parameter

Sel1_size

=

3;parameter

Sel2_size

=

2;wire

[Sel1_size-1:

0]

Sel_Bus_1_Mux;wire

[Sel2_size-1:

0]

Sel_Bus_2_Mux;input

clk,

rst;//

Data

Netswire

zero;wire

[word_size-1:

0]

instruction,

address,

Bus_1,

mem_word;//

Control

Netswire

Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC,

Load_IR;wire

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z;wire

write;Processing_Unit

M0_Processor

(instruction,

zero,

address,

Bus_1,

mem_word,

Load_R0,

Load_R1,Load_R2,

Load_R3,

Load_PC,

Inc_PC,

Sel_Bus_1_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,Load_Reg_Z,

Sel_Bus_2_Mux,

clk,

rst);Control_Unit

M1_Controller

(Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC,Sel_Bus_1_Mux,Sel_Bus_2_Mux

,

Load_IR,Load_Add_R,Load_Reg_Y,

Load_Reg_Z,write,

instruction,

zero,

clk,

rst);Memory_Unit

M2_SRAM

(

.data_out(mem_word),

.data_in(Bus_1),

.address(address),.clk(clk),

.write(write)

);endmoduleRISC

CPU

設(shè)計實例module

Processing_Unit

(instruction,

Zflag,

address,

Bus_1,

mem_word,

Load_R0,

Load_R1,

Load_R2,Load_R3,

Load_PC,

Inc_PC,

Sel_Bus_1_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z,Sel_Bus_2_Mux,clk,

rst);parameter

word_size

=

8;parameter

op_size

=

4;parameter

Sel1_size

=

3;parameter

Sel2_size

=

2;output

[word_size-1:

0]outputinput

[word_size-1:

0]inputinput[Sel1_size-1:

0]input[Sel2_size-1:

0]inputinputwirewire

[word_size-1:

0]wire

[word_size-1:

0]wire

[word_size-1:

0]wirewire

[op_size-1

:

0]instruction,

address,

Bus_1;Zflag;mem_word;Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC;Sel_Bus_1_Mux;Sel_Bus_2_Mux;Load_IR,

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z;clk,

rst;Load_R0,

Load_R1,

Load_R2,

Load_R3;Bus_2;R0_out,

R1_out,

R2_out,

R3_out;PC_count,

Y_value,

alu_out;alu_zero_flag;opcode

=

instruction

[word_size-1:

word_size-op_size];RISC

CPU

設(shè)計實例module

Processing_Unit

(instruction,

Zflag,

address,

Bus_1,

mem_word,

Load_R0,

Load_R1,

Load_R2,Load_R3,

Load_PC,

Inc_PC,

Sel_Bus_1_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,Load_Reg_Z,Sel_Bus_2_Mux,clk,

rst);（續(xù)）Register_UnitR0(R0_out,

Bus_2,

Load_R0,

clk,

rst);Register_UnitR1(R1_out,

Bus_2,

Load_R1,

clk,

rst);Register_UnitR2(R2_out,

Bus_2,

Load_R2,

clk,

rst);Register_UnitR3(R3_out,

Bus_2,

Load_R3,

clk,

rst);Register_UnitReg_Y(Y_value,

Bus_2,

Load_Reg_Y,

clk,

rst);D_flopReg_Z(Zflag,

alu_zero_flag,

Load_Reg_Z,

clk,rst);Address_RegisterAdd_R(address,

Bus_2,

Load_Add_R,

clk,

rst);Instruction_RegisterIR(instruction,

Bus_2,

Load_IR,

clk,

rst);Program_CounterPC(PC_count,

Bus_2,

Load_PC,

Inc_PC,

clk,

rst);Multiplexer_5chMux_1(Bus_1,

R0_out,

R1_out,

R2_out,

R3_out,

PC_count,

Sel_Bus_1_Mux);Multiplexer_3chMux_2(Bus_2,

alu_out,

Bus_1,

mem_word,

Sel_Bus_2_Mux);(alu_zero_flag,

alu_out,

Y_value,

Bus_1,opcode);Alu_RISC

ALUendmoduleRISC

CPU

設(shè)計實例module

Register_Unit

(data_out,

data_in,

load,

clk,

rst);parameteroutput

[word_size-1:

0][word_size-1:

0]inputinputinputreg[word_size-1:

0]word_size

=

8;data_out;data_in;load;clk,rst;data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load)

data_out

<=

data_in;endmodulemodule

D_flop

(data_out,

data_in,

load,

clk,

rst);outputinputinputinputregdata_out;data_in;load;clk,rst;data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load

==

1)data_out

<=

data_in;endmoduleRISC

CPU

設(shè)計實例module

Address_Register

(data_out,

data_in,

load,

clk,rst);parameter

word_size

=8;output

[word_size-1:

0]

data_out;input[word_size-1:

0]data_in;inputload,

clk,

rst;reg[word_size-1:

0]data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load)

data_out

<=

data_in;endmodulemodule

Instruction_Register(data_out,

data_in,

load,

clk,

rst);parameter

word_size

=8;output

[word_size-1:

0]

data_out;input[word_size-1:

0]data_in;inputload;inputclk,rst;reg[word_size-1:

0]data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load)

data_out

<=

data_in;endmoduleRISC

CPU

設(shè)計實例module

Program_Counter

(count,

data_in,

Load_PC,

Inc_PC,

clk,

rst);parameter

word_size

=8;output

[word_size-1:

0]

count;input[word_size-1:

0]data_in;inputLoad_PC,

Inc_PC;inputclk,rst;reg[word_size-1:

0]count;always

@

(posedgeclkor

negedgerst)if

(rst

==

0)

count

<=0;

else

if

(Load_PC)

count<=data_in;else

if

(Inc_PC)count<=count+1;endmoduleRISC

CPU

設(shè)計實例module

Multiplexer_5ch

(mux_out,

data_a,data_b,

data_c,

data_d,

data_e,sel);parameter

word_size

=8;output

[word_size-1:

0]mux_out;data_a,

data_b,

data_c,data_d,data_e;inputinput[word_size-1:

0][2:

0]

sel;?data_a:(sel

==1)assign

mux_out=(sel

==0)?

data_b

:

(sel

==

2)?

data_c:

(sel

==

3)?

data_d

:

(sel

==

4)?

data_e

:

'bx;endmodulemodule

Multiplexer_3ch

(mux_out,

data_a,

data_b,

data_c,

sel);parameterword_size

=

8;output[word_size-1:

0]mux_out;input[word_size-1:

0]data_a,

data_b,

data_c;input[1:

0]

sel;assign

mux_out

=

(sel

==

0)

?

data_a:

(sel

==

1)

?

data_b

:

(sel

==

2)

?

data_c:

'bx;endmoduleRISC

CPU

設(shè)計實例module

Alu_RISC

(alu_zero_flag,

alu_out,

data_1,

data_2,

sel);parameter

word_size

=

8;parameter

op_size

=

4;//

Opcodes=4'b0000;=4'b0001;=4'b0010;=4'b0011;=4'b0100;parameter

NOPparameter

ADDparameter

SUBparameter

ANDparameter

NOTparameter

RDparameter

WRparameter

BRparameter

BRZoutputoutput

[word_size-1:

0]input

[word_size-1:

0]input

[op_size-1:

0]reg

[word_size-1:

0]=

4'b0101;=4'b0110;=

4'b0111;=4'b1000;alu_zero_flag;alu_out;data_1,

data_2;sel;alu_out;assign

alu_zero_flag

=~|alu_out;always

@

(sel

or

data_1

or

data_2)case

(sel)NOP: alu_out

=

0;ADD:SUB:AND:alu_out

=

data_1

+

data_2;

//

Reg_Y

+

Bus_1alu_out

=

data_2

-

data_1;alu_out

=

data_1

&

data_2;NOT: alu_out

=

~

data_2;//

Gets

data

from

Bus_1default:

alu_out

=

0;endcaseendmoduleRISC

CPU

設(shè)計實例module

Control_Unit

(

Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC,Sel_Bus_1_Mux,

Sel_Bus_2_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z,write,

instruction,

zero,

clk,

rst);parameter

word_size

=

8,

op_size

=

4,

state_size

=4;parameter

src_size

=

2,

dest_size

=

2,

Sel1_size

=

3,

Sel2_size

=

2;//

State

Codesparameter

S_idle

=

0,

S_fet1

=

1,

S_fet2

=

2,

S_dec

=3;parameter

S_ex1

=

4,

S_rd1

=

5,

S_rd2

=6;parameter

S_wr1

=

7,

S_wr2

=

8,

S_br1

=

9,

S_br2

=

10,

S_halt

=

11;//

Opcodesparameter

NOP

=

0,

ADD

=

1,

SUB

=2,

AND

=

3,

NOT

=

4;parameter

RD

=

5,

WR

=

6,

BR

=

7,

BRZ=

8;//

Source

and

Destination

Codesparameter

R0

=

0,

R1

=

1,

R2

=

2,

R3

=

3;output

Load_R0,

Load_R1,

Load_R2,

Load_R3;output

Load_PC,

Inc_PC;output

[Sel1_size-1:0]

Sel_Bus_1_Mux;output

Load_IR,

Load_Add_R;output

Load_Reg_Y,

Load_Reg_Z;output

[Sel2_size-1:

0]

Sel_Bus_2_Mux;output

write;input

[word_size-1:

0]

instruction;input

zero;input

clk,

rst;RISC

CPU

設(shè)計實例reg

[state_size-1:

0]

state,

next_state;reg

Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC;reg

Load_IR,

Load_Add_R,

Load_Reg_Y;reg

Sel_ALU,

Sel_Bus_1,

Sel_Mem;reg

Sel_R0,

Sel_R1,

Sel_R2,

Sel_R3,

Sel_PC;reg

Load_Reg_Z,

write;reg

err_flag;wire

[op_size-1:0]

opcode

=

instruction

[word_size-1:

word_size

-

op_size];wire

[src_size-1:

0]

src

=

instruction

[src_size

+

dest_size

-1:

dest_size];wire

[dest_size-1:0]

dest

=

instruction

[dest_size

-1:0];//

Mux

selectorsassign

Sel_Bus_1_Mux[Sel1_size-1:0]

=

Sel_R0

?

0:Sel_R1

?

1:Sel_R2

?

2:Sel_R3

?

3:Sel_PC

?

4:

3'bx;

//

3-bits,

sized

numberassign

Sel_Bus_2_Mux[Sel2_size-1:0]

=

Sel_ALU

?

0:Sel_Bus_1

?

1:Sel_Mem

?

2:

2'bx;always

@

(posedge

clk

or

negedge

rst)

begin:

State_transitionsif

(rst

==

0)

state

<=

S_idle;

else

state

<=

next_state;

endRISC

CPU

設(shè)計實例always

@

(state

or

opcode

or

zero)

begin:

Output_and_next_stateSel_R0

=

0;

Sel_R1

=

0;Sel_R2

=

0;Sel_R3

=

0;Sel_PC

=0;Load_R0

=

0;Load_R1

=

0;Load_R2

=

0;Load_R3

=

0;Load_PC

=

0;Load_IR

=

0;Load_Add_R

=

0;Load_Reg_Y

=

0;Load_Reg_Z

=

0;Inc_PC

=

0;Sel_Bus_1

=

0;Sel_ALU

=

0;Sel_Mem

=

0;write

=

0;//

Used

for

de-bug

in

simulationerr_flag

=

0;next_state

=

state;case

(state)S_idle:S_fet1:S_fet2:next_state

=

S_fet1;beginnext_state

=

S_fet2;Sel_PC

=1;Sel_Bus_1

=

1;Load_Add_R=

1;endbeginnext_state

=

S_dec;Sel_Mem

=

1;Load_IR

=

1;Inc_PC

=

1;endRISC

CPU

設(shè)計實例case

(state)S_dec:case

(opcode)NOP: next_state

=

S_fet1;ADD,

SUB,

AND:

beginnext_state

=

S_ex1;

Sel_Bus_1

=

1;

Load_Reg_Y

=1;case

(src)Sel_R0

=

1;Sel_R1

=

1;Sel_R2

=

1;Sel_R3

=

1;err_flag

=

1;R0:R1:R2:R3:default

:endcaseend

//

ADD,

SUB,

ANDRISC

CPU

設(shè)計實例NOT:Sel_R0

=

1;Sel_R1

=

1;Sel_R2

=

1;Sel_R3

=

1;err_flag

=

1;beginnext_state

=

S_fet1;Load_Reg_Z

=

1;Sel_Bus_1

=

1;Sel_ALU

=

1;case

(src)R0:R1:R2:R3:default

:endcasecase

(dest)R0:R1:R2:R3:Load_R0

=

1;Load_R1

=

1;Load_R2

=

1;Load_R3

=

1;RD:default:

err_flag

=

1;endcaseend

//NOTbeginnext_state

=

S_rd1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//RDRISC

CPU

設(shè)計實例WR:BR:BRZ:beginnext_state

=

S_wr1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//

WRbeginnext_state

=

S_br1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//

BRif

(zero

==

1)

beginnext_state

=

S_br1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//

BRZelse

beginnext_state

=

S_fet1;Inc_PC

=

1;endnext_state

=

S_halt;default

:endcase

//

(opcode)RISC

CPU

設(shè)計實例case

(state)S_ex1:S_rd1:S_wr1:beginnext_state

=

S_fet1;Load_Reg_Z

=

1;Sel_ALU

=

1;case

(dest)R0:

begin

Sel_R0

=

1;

Load_R0