EDA第5章 作業(yè)講解

第5章作業(yè)講解LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdecoder38IS

PORT(din:INSTD_LOGIC_VECTOR(2DOWNTO0);en:INSTD_LOGIC;

xout:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDdecoder38;設(shè)計一個3-8譯碼器，實體名decoder38。輸入端口：din輸入端，位寬為3位

en譯碼器輸出使能，高電平有效輸出端口：xout

譯碼器輸出，低電平有效ARCHITECTUREbhavOFdecoder38IS BEGIN

PROCESS(din,en)BEGIN

IF(en='1')THENCASEdinISWHEN"000"=>xout<="11111110";WHEN"001"=>xout<="11111101";WHEN"010"=>xout<="11111011";WHEN"011"=>xout<="11110111";WHEN"100"=>xout<="11101111";WHEN"101"=>xout<="11011111";WHEN"110"=>xout<="10111111";WHEN"111"=>xout<="01111111";WHENOTHERS=>xout<="11111111";ENDCASE;ELSE

xout<="11111111";ENDIF;ENDPROCESS;ENDbhav;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYS_C74161IS

PORT(clk,ldn,clrn,enp,ent:INSTD_LOGIC;

din:INSTD_LOGIC_VECTOR(3DOWNTO0);q:OUTSTD_LOGIC_VECTOR(3DOWNTO0);

rco:OUTSTD_LOGIC);ENDS_C74161;用VHDL描述下列器件的功能：（1）集成計數(shù)器74161ARCHITECTURE

behav

OFS_C74161IS

SIGNAL

tmp:STD_LOGIC_VECTOR(3DOWNTO0);BEGIN

PROCESS(clk,clrn)

BEGIN

IF

clrn='0'THEN

tmp<="0000";

ELSIF(clk'EVENT

AND

clk='1')THEN

IF

ldn='0'THEN

tmp<=din;

ELSIF(enp='1'andent='1')THEN

tmp<=tmp+1;

END

IF;

END

IF; q<=tmp;

END

PROCESS;

rco<=tmp(3)and

tmp(2)and

tmp(1)and

tmp(0)and

ent;END

behav;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYS_R74194IS

PORT(clrn,clk,slsi,srsi:INSTD_LOGIC;

din:INSTD_LOGIC_VECTOR(3DOWNTO0);

ss:IN

STD_LOGIC_VECTOR(1DOWNTO0);

q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDS_R74194;（2）集成移位寄存器74194ARCHITECTUREbhvOFS_R74194ISSIGNALtmp:STD_LOGIC_VECTOR(3DOWNTO0);BEGIN

PROCESS(clk,clrn)BEGIN

IF(clrn='0')THEN

tmp<="0000";

ELSIF(clk'EVENTANDclk='1')THEN

IF(ss="11")THEN

tmp<=din;

ELSIF(ss="01")THEN

tmp<=srsi&tmp(3downto1);

ELSIF(ss="10")THEN

tmp<=tmp(2downto0)&slsi;ENDIF;ENDIF;q<=tmp;ENDPROCESS;ENDbhv;一位全減器的算法描述、數(shù)據(jù)流描述、結(jié)構(gòu)描述ENTITY

f_sub

IS

PORT(x,y,sub_in:INSTD_LOGIC;

sub_out,diff:OUTSTD_LOGIC);END

f_sub;（1）算法描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ARCHITECTURE

bhv

OF

f_sub

IS

SIGNALtmp:STD_LOGIC_VECTOR(2DOWNTO0);BEGIN

tmp<=x&y&sub_in;

PROCESS(tmp)

BEGIN

CASE

tmp

IS

WHEN"000"=>diff<='0';sub_out<='0';

WHEN"001"=>diff<='1';sub_out<='1';

WHEN"010"=>diff<='1';sub_out<='1';

WHEN"011"=>diff<='0';sub_out<='1';

WHEN"100"=>diff<='1';sub_out<='0';

WHEN"101"=>diff<='0';sub_out<='0';

WHEN"110"=>diff<='0';sub_out<='0';

WHEN"111"=>diff<='1';sub_out<='1';

WHENOTHERS=>NULL;

END

CASE;

END

PROCESS;END

bhv;ENTITY

f_sub

IS

PORT(x,y,sub_in:INSTD_LOGIC;

sub_out,diff:OUTSTD_LOGIC);END

f_sub;ARCHITECTURE

rtl

OF

f_sub

IS

BEGINdiff<=xXORyXOR

sub_in;

sub_out<=(NOTxANDy)OR((xXNORy)AND

sub_in);END

rtl;（2）數(shù)據(jù)流描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;--半加器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITY

h_sub

IS

PORT(a,b:INSTD_LOGIC;

co,so:OUTSTD_LOGIC);END

h_sub;ARCHITECTUREfh1OF

h_sub

ISBEGINso<=aXORb;co<=NOTaANDb;ENDfh1;（3）結(jié)構(gòu)描述--或門描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2aIS

PORT(a,b:INSTD_LOGIC;

c:OUT

STD_LOGIC);ENDor2a;ARCHITECTUREoneOFor2aISBEGIN c<=aORb;ENDone;LIBRARYIEEE;--全減器描述USE

IEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYf_sub1IS

PORT(x,y,sub_in:INSTD_LOGIC;

sub_out,diff:OUTSTD_LOGIC);ENDf_sub1;ARCHITECTURE

strl

OFf_sub1ISCOMPONENT

h_sub

PORT(a,b:INSTD_LOGIC;

co,so:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor2a

PORT(a,b:INSTD_LOGIC;

c:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC;BEGINu1:h_subPORT

MAP(x,y,d,e);u2:h_subPORT

MAP(e,sub_in,f,diff);u3:or2aPORT

MAP(d,f,sub_out);END

strl;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYfp1000IS

PORT(clkin:INSTD_LOGIC;

clkout:OUTSTD_LOGIC);ENDfp1000;用VHDL設(shè)計實現(xiàn)輸出占空比為50%的1000分頻器。下列VHDL程序描述帶復(fù)位和預(yù)置控制的85進制加法計數(shù)器cnt_85，設(shè)電路的預(yù)置數(shù)據(jù)輸入端為d[6..0]，記數(shù)輸出端為q[6..0]。時鐘輸入端為clk。cr是異步清零輸入端，ld為同步預(yù)置數(shù)控制端，en為使能控制輸入端。當cr=0時，q[6..0]=0000000，當ld=0時，q[6..0]=d[6..0]，當en=0時，計數(shù)器保持不變，而當en=1時，計數(shù)器計數(shù)。cout為計數(shù)器進位輸出。其實體框圖如下圖所示。crclkldrd[6..0]q[6..0]encoutcnt_85LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcnt_85IS

PORT(clk,ld,cr,en:INSTD_LOGIC;

d:INSTD_LOGIC_VECTOR(6DOWNTO0);q:OUTSTD_LOGIC_VECTOR(6DOWNTO0);

cout:OUTSTD_LOGIC);ENDcnt_85;ARCHITECTUREbehavOFcnt_85ISSIGNALtmp:STD_LOGIC_VECTOR(6DOWNTO0);BEGIN

PROCESS(clk,cr)BEGINIFcr='0'THEN

tmp<="0000000";ELSIF(clk'EVENTANDclk='1')THENIFld='0'THEN

tmp<=d;ELSIF(en='1')THEN