計算機組成教學(xué)課件：Chapter8 MemorySystem

Chapter8

TheMemorySystem2Contents8.1TheMemorySystemOverview8.2SemiconductorRAMMemories8.3ReadOnlyMemories8.4MemoryHierarchy8.5CacheMemories8.6VirtualMemory8.7SecondaryStorageSummary38.1TheMemorySystemOverviewInternalMemoryandExternalMemoryThetypicalcomputersystemisequippedwithahierarchyofmemorysubsystems.InternalMemory(PrimaryStorage)Internaltothesystem,directlyaccessiblebytheprocessor.Example:MainMemory,Cache,ProcessorRegistersExternalMemory(SecondaryStorage)Externaltothesystem,accessiblebytheprocessorviaanI/Omodule.4BasicConceptsMemoryLocationsandAddressesHowthememoryisorganized?Example:

Threewaysoforganizinga96-bitmemory5BasicConceptsMemoryLocationsandAddressesHowthememoryisorganized?Thememoryconsistsofmanymillionsofstoragecells,eachofwhichcanstoreabitofinformationhavingthevalue0or1.Thememoryisorganizedsothatagroupoffixedsizeofbitscanbestoredorretrievedinasingle,basicmemoryoperation.Word:Eachgroupoffixedsizeofbitsisreferredtoasaword.Wordlength:Thenumberofbitsineachwordisreferredtoaswordlength.Ittypicallyrangesfrom16to64bits.6Figure2.2.

Examplesofencodedinformationina32-bitword.(b)Fourcharacterscharactercharactercharactercharacter(a)AsignedintegerSignbit:

forpositivenumbers

fornegativenumbersASCIIASCIIASCIIASCII32bits8bits8bits8bits8bitsb31b30b1b0b310=b311=???Example:a32-bitword7BasicConceptsMemoryLocationsandAddressesHowthememoryisorganized?Thememoryofacomputercanbeschematicallyrepresentedasacollectionofwords.8BasicConceptsMemoryLocationsandAddressesAddressandAddressSpaceAddressesarenumbersthatidentifymemorylocations.Itiscustomarytousenumbersfrom0through2k–1,forsomesuitablevalueofk,astheaddressesofsuccessivelocationsinthememory.The2kaddressesconstitutetheaddressspaceofthecomputer,andthememorycanhaveupto2kaddressablelocations.ByteAddressabilityThreebasicinformationquantities:BitByte:8bitsWord:Wordlengthrangesfrom16to64bits9BasicConceptsMemoryLocationsandAddressesByteAddressabilityByte-addressableMemoryThemostpracticalassignmentistohavesuccessiveaddressesrefertosuccessivebytelocationsinthememory.Big-endianAssignmentInthisassignment,thelowerbyteaddressesareusedforthemoresignificantbytes(theleftmostbytes)oftheword.Example:

Big-endianassignmentfor32-bitword-lengthbyte-addressablememory.Little-endianAssignmentInthisassignment,thelowerbyteaddressesareusedforthelesssignificantbytes(therightmostbytes)oftheword.Example:

Little-endianassignment10BasicConceptsMemoryLocationsandAddressesByteAddressabilityBig-endianAssignmentandLittle-endianAssignmentNote:Inbothcases,byteaddresses0,4,8,…,aretakenastheaddressesofsuccessivewordsinthememoryandaretheaddressesusedwhenspecifyingmemoryoperationsforwords.11BasicConceptsMemoryLocationsandAddressesBitAddressabilitySpecifytheLabelingofbitswithinabyteSpecifytheLabelingofbitswithinaword12BasicConceptsMemoryLocationsandAddressesWordAlignmentWordsaresaidtobealignedinmemoryiftheybeginatabyteaddressthatisamultipleofthenumberofbytesinaword.Wordaresaidtobeunalignedinmemoryiftheybeginatanarbitrarybyteaddress.AccessingNumbers,Characters,andCharacterStringsNumbers:specifytheirwordaddressesIndividualcharacters:specifytheirbyteaddressesCharacterStringsofVariableLength:givethebyteaddresscontainingthefirstcharacter,lengthofthestring13BasicConceptsMemoryOperationsConnectionofthememorytotheprocessor14BasicConceptsMemoryOperationsReadTransfersacopyofthecontentsofaspecificmemorylocationtotheprocessor.Processor:Sendstheaddressofthedesiredlocationtothememoryandrequeststhatitscontentsberead.Memory:Readsthedatastoredatthataddressandsendsthemtotheprocessor.15BasicConceptsMemoryOperationsWriteTransferanitemofinformationfromtheprocessortoaspecificlocation,overwritingtheformercontentsofthatlocation.Processor:Sendstheaddressofthedesiredlocationtothememory,togetherwiththedatatobewrittenintothatlocation.Memory:Usetheaddressanddatatoperformthewrite.16CharacteristicsofMemorySystemsCapacityInternalmemory:usuallyexpressedintermsofnumbersofbytesorwords.Externalmemory:usuallyexpressedintermsofnumbersofbytes.UnitofTransfer:Numberofbitsreadfrom,orwrittenintomemoryatatime.Internalmemory:usuallyequaltothenumberofdatalinesintoandoutofthememorymodule.Itisoftenequaltothenumberofthewordlength,butitmaynotbe.Externalmemory:dataareoftentransferredinmuchlargerunitsthanaword,andthesearereferredtoasblocks.17CharacteristicsofMemorySystemsMethodofAccessingSequentialAccessMemoryisorganizedintounitsofdata,calledrecords.Accessmustbemadeinaspecificlinearsequence.Thetimetoaccessanarbitraryrecordishighlyvariable.Example:MagneticTapeDirectAccessIndividualblocksorrecordshaveauniqueaddressbasedonphysicallocation.Accessisaccomplishedbydirectaccesstoreachageneralvicinityplussequentialsearching,countingorwaitingtoreachthefinallocation.Accesstimeisvariable.Example:

MagneticDisk18CharacteristicsofMemorySystemsMethodofAccessingRandomAccessAnymemorylocationcanbeselectedatrandomanddirectlyaddressedandaccessed.Thetimetoaccessagivenlocationisindependentofthelocation’saddressandisconstant.Example:

RAMAssociativeAccessAwordisretrievedbasedonaportionofitscontentsratherthanitsaddress.AccesstimeisindependentoflocationorpreviousaccessExample:

Cache19CharacteristicsofMemorySystemsPerformance(Speed)AccessTimeTimebetweenpresentingtheaddressandgettingthevaliddata(memoryorotherstorage)

Random-accessmemory:Thetimeittakestoperformareadorwriteoperation.Non-random-accessmemory:Thetimeittakestopositiontheread-writemechanismatthedesiredlocation.MemoryCycleTime(forrandomaccessmemory)Itconsistsoftheaccesstimeplusanyadditionaltimerequiredbeforeasecondaccesscancommence.MemoryCycleTime=AccessTime+RecoveryTimeNote:Accesstimeandmemorycycletimeareallmeasuresofthespeedofmemoryunits.20CharacteristicsofMemorySystemsPerformance(Speed)TransferRateItistherateatwhichdatacanbetransferredintooroutofamemoryunit.Random-accessmemory:itisequalto1/(cycletime).Non-random-accessmemory,therelationshipisTN=TA+N/R,where

TN:AveragetimetoreadorwriteNbits, TA:Averageaccesstime, N:Numberofbits, R:Transferrate,inbitspersecond(bps).21CharacteristicsofMemorySystemsPhysicalTypesSemiconductorExample:MainMemoryMagneticSurfaceExample:MagneticdiskandMagnetictapeOptical22CharacteristicsofMemorySystemsPhysicalCharacteristicVolatile/NonvolatileVolatile:Informationdecaysnaturallyorislostwhenelectricalpowerisswitchedoff.Nonvolatile:Informationoncerecordedremainswithoutdeteriorationuntildeliberatelychanged.Noelectricalpowerisneededtoretaininformation.Example:Magneticsurfacememoriesarenonvolatile.Semiconductormemorymaybeeithervolatileornonvolatile.Erasable/NonerasableErasable:Thecontentsofthememorycanbealtered.Nonerasable:Thecontentsofthememorycannotbealtered,exceptbydestroyingthestorageunit.238.2SemiconductorRAMMemoriesSemiconductorRAMMemoryThemostcommontypeofsemiconductormemoryisreferredtoasrandom-accessmemory(RAM).CharacteristicItispossiblebothtoreaddatafromthememoryandtowritenewdataintothememoryeasilyandrapidlyItisvolatile.Accesstimeisofjustafewnanoseconds.24RAMTechnologyStaticTechnologyInastaticRAM,binaryvaluesarestoredusingtraditionalflip-floplogic-gateconfigurations.DynamicTechnologyAdynamicRAMismadewithcellsthatstoredataaschargeoncapacitors.Thepresenceorabsenceofchargeinacapacitorisinterpretedasabinary1or0.NoteBothstaticRAMsanddynamicRAMsarevolatile.25StaticRAM(SRAM)ImplementationofaSRAMcellYXWordlineBitlinesFigure8.4.AstaticRAMcell.bT2T1b￠26StaticRAM(SRAM)ImplementationofaSRAMcellAssumethatthecellisinstate1ifthelogicvalueatpointXis1andatpointYis0.ReadOperationThewordlineisathighlevel.Read“1”:Thesignalonthebitlinebishighandthesignalonthebitlineb’islow.Read“0”:Thesignalonthebitlinebislowandthesignalonthebitlineb’ishigh.Note:Sense/writecircuitsattheendofthebitlinesmonitorthestateofbandb’andsettheoutputaccordingly.27StaticRAM(SRAM)ImplementationofaSRAMcellWriteOperationThewordlineisathighlevel.Write“1”:Placehighlevelsignalonbitlinebandplacelowlevelsignalonbitlineb’.Write“0”:Placehighlevelsignalonbitlinebandplacelowlevelsignalonbitlineb’.Note:TherequiredsignalsonthebitlinesaregeneratedbytheSense/Writecircuit.MaintainStateThewordlineisatgroundlevel.28StaticRAM(SRAM)CMOSRealizationofaSRAMcellMOSICNMOSCMOS: Complementary Metal-Oxide Semiconductor29StaticRAM(SRAM)CMOSRealizationofaSRAMcellThepowersupplyvoltageis5VinolderCMOSSRAMsor3.3Vinnewlow-voltageversions.Ifpowerisinterruptedandthenitisrestored,thelatchwillsettleintoastablestate,butitwillnotnecessarilybethesamestatethecellwasinbeforetheinterruption.CMOSSRAMs’powerconsumptionisverylow.AdvantageandDisadvantageofStaticRAMAdvantage:FastDisadvantage:Lowdensity,Highcost30InternalOrganizationofStaticRAMChips

Organizationof128BitCells(16×8)FFFigure8.2.

Organizationofbitcellsinamemorychip.circuitSense/WriteAddressdecoderFFCScellsMemorycircuitSense/WriteSense/WritecircuitDatainput/outputlines:A0A1A2A3W0W1W15b7b1b0WR/b￠7b￠1b￠0b7b1b0???????????????????????????31InternalOrganizationofStaticRAMChips

Organizationof128BitCells(16×8)InternalOrganizationWordline:Allcellsofarowareconnectedtothewordline.Itisdrivenbytheaddressdecoder.Bitlines:ThecellsineachcolumnareconnectedtoaSense/Writecircuitbytwobitlines.Sense/Writecircuits:Read:Theysensetheinformationstoredinthecellsselectedbyawordlineandtransmitthisinformationtotheoutputdatalines.Write:Theyreceiveinputinformationandstoreitinthecellsoftheselectedword.32InternalOrganizationofStaticRAMChips

Organizationof128BitCells(16×8)ExternalConnectionsAddresslines(Input):A0–A3Datalines(Input/Output):b0–b7Controllines(Input)R/W(Read/Write):SpecifytherequiredReadorWriteoperation.CS(ChipSelect):Selectagivenchipinamulti-chipmemorysystem.PowerSupplylineGroundlineTotalConnections=4+8+2+1+1=1633InternalOrganizationofStaticRAMChips

Organizationof1024(1K)BitCells128×8OrganizationExternalConnectionsAddresslines(Input):A0–A6Datalines(Input/Output):b0–b7Controllines(Input):R/W,CSPowersupplylineGroundlineTotalConnections=7+8+2+1+1=1934InternalOrganizationofStaticRAMChips

Organizationof1024(1K)BitCells1K×1OrganizationFigure8.3.Organizationofa1K1memorychip.CSSense/Writecircuitryarraymemorycelladdress5-bitrowinput/outputData5-bitdecoderaddress5-bitcolumnaddress10-bitoutputmultiplexer32-to-1inputdemultiplexer3232×WR/W0W1W31and35InternalOrganizationofStaticRAMChips

Organizationof1024(1K)BitCells1K×1OrganizationExternalConnectionsAddresslines(Input):A0–A9Datalines(Input/Output):b0Controllines(Input):R/W,CSPowersupplylineGroundlineTotalConnections=10+1+2+1+1=15LargechipshaveessentiallythesameorganizationasFigure8.3butusealargermemorycellarrayandhavemoreexternalconnections.36StaticRAMChips

ExampleDIP(DualIn-linePackages, 雙列直插封裝。中小規(guī)模集 成電路均采用這種封裝形式， 其引腳數(shù)一般不超過100)37StaticRAMChips

ExampleReadOperationPlacetheaddressofthebittobereadontheaddresspinsviatheaddressbus.(MakesureWriteEnableisnotactivewhenthishappens,sothattheSRAMknowsit'snotbeingwrittento.)ActivateChipSelecttoselecttheSRAMchip.WriteOperationPlacetheaddressofthecelltobewrittentoontheaddresspinsviatheaddressbus.Placethebitthatyou'regoingtowriteontheDataInpinviathedatabus.ActivateChipSelecttoselecttheSRAMchip.ActivateWriteEnablesothattheSRAMknowsit'sbeingwrittento.38DynamicRAMExampleofaDRAMcellFigure8.6.

Asingle-transistordynamicmemorycell

TCWordlineBitline39DynamicRAMExampleofaDRAMcellMaintainStateThewordlineislow.ReadOperationThewordlineishigh.Read“1”:Ifthechargestoredonthecapacitorisabovethethresholdvalue,thesenseamplifierdrivesthebitlinetoafullvoltagethatrepresents“1”.Thisvoltagerechargesthecapacitortothefullchargethatcorrespondsto“1”.Read“0”:Ifthechargestoredonthecapacitorisbelowthethresholdvalue,thesenseamplifierpullsthebitlinetogroundlevel,whichensuresthatthecapacitorwillhavenocharge,representing“0”.40DynamicRAMExampleofaDRAMcellWriteOperationThewordlineishigh.Write“1”:Thebitlineisappliedhighvoltage.Write“0”:Thebitlineisappliedlowvoltage.RefreshReadingthecontentsofaDRAMcellautomaticallyrefreshesitscontents.DisadvantageLongeraccesstimesLeaky,needstoberefreshedCannotbeeasilyintegratedwithCMOS41DynamicRAMInternalOrganizationofanAsynchronousDRAMChipExample: 16MDRAM

(2M×8)ColumnCSSense/WritecircuitscellarraylatchaddressRowColumnlatchdecoderRowdecoderaddress40965128×()×R/WA209-A80-¤D0D7RASCASFigure8.7.Internalorganizationofa2M×8dynamicmemorychip.42DynamicRAMInternalOrganizationofanAsynchronousDRAMChipExample(ctd.)12bitaddressbitsareneededtoselectarow.Another9bitsareneededtospecifyagroupof8bitsintheselectedrow.Total:21-bitaddressToreducethenumberofpinsneededforexternalconnections,therowandcolumnaddressesaremultiplexedon12pins.RowAddressStrobe(RAS)ColumnAddressStrobe(CAS)43DynamicRAMInternalOrganizationofanAsynchronousDRAMChipExample(ctd.):ReadOperationTherowaddressisplacedontheaddresspinsviatheaddressbus.TheRASpinisactivated,whichplacestherowaddressontotheRowAddressLatch.TheRowAddressDecoderselectstheproperrowtobesenttothesenseamplifiers.TheWriteEnableisdeactivated,sotheDRAMknowsthatit'snotbeingwrittento.Thecolumnaddressisplacedontheaddresspinsviatheaddressbus.44DynamicRAMInternalOrganizationofanAsynchronousDRAMChipExample(ctd.):ReadOperationTheCASpinisactivated,whichplacesthecolumnaddressontheColumnAddressLatch.

TheCASpinalsoservesastheOutputEnable,sooncetheCASsignalhasstabilizedthesenseamplifiersplacethedatafromtheselectedrowandcolumnontheDataOutpinsothatitcantravelthedatabusbackoutintothesystem.RASandCASarebothdeactivatedsothatthecyclecanbeginagain.45DynamicRAMDRAMRefreshLeakystoragePeriodicrefreshacrossDRAMrowsApplyingarowaddresscausesallcellsonthecorrespondingrowtobereadandrefreshedduringbothReadandWriteoperations.RefreshmentofaDRAMchipcanbeaccomplishedbyaccessingeachrowofcellsperiodically.TheDRAMcontrollerperiodicallysweepsthroughalloftherowsbycyclingRASrepeatedlyandplacingaseriesofrowaddressesontheaddressbus.46DynamicRAMDRAMRefreshUn-accessiblewhenrefreshingExample:4KrowsinaDRAM,100nsreadcycle,Decayin64ms4096*100ns=410μstorefreshonce410μs/64ms=0.64%unavailability47DynamicRAMDRAMRefreshRefreshStylesBurstyDistributed48DynamicRAMChipsExampleIntel2118:16K×1DifferentcontrolsignalsthanSRAMchipsRequiresonly1/2numberofinputaddresslines(AddressMultiplexing)ReplacedCSbyRASandCAS(verystricttimingconstraints)Separatesdatainputsandoutputs(typically)49DynamicRAMChipsExample:readsequencing50AsynchronousDRAMThetimingofthememoryiscontrolledasynchronously.Normal:RespondstoRASandCASsignals(noclock)Aspecializedmemorycontrollercircuitprovidesthenecessarycontrolsignals,RASandCASthatgovernthetiming.51AsynchronousDRAMQuestion:HowtoaccesstheotherbytesinthesamerowofaDRAMchip?Reselecttherow,andthenrepeatthereadprocessforreadingtheotherbyteinthesamerow.52AsynchronousDRAMQuestion:HowtoaccesstheotherbytesinthesamerowofaDRAMchip?Withoutreselectingtherow,addalatchtotheoutputofthesenseamplifierineachcolumn.ItisonlytoapplydifferentcolumnaddressesunderthecontrolofsuccessiveCASsignalstoplacethedifferentbytesonthedatalines.53AsynchronousDRAMFastPageMode(FPM)RowremainsopenafterRASformultipleCAScommandsItallowstransferringablockofdataatamuchfasterratethancanbeachievedfortransfersinvolvingrandomaddresses.54SynchronousDRAMs(SDRAMs)Theiroperationisdirectlysynchronizedwithaclocksignal.StructureofaSDRAMChipR/WRASCASCSClockCellarraylatchaddressRowdecoderRowFigure8.8.

SynchronousDRAM.decoderColumnRead/Writecircuits&latchescounteraddressColumnRow/ColumnaddressDatainputregisterDataoutputregisterDataRefreshcounterModeregisterandtimingcontrol55SynchronousDRAMs(SDRAMs)StructureofaSDRAMChip(ctd.)Ifanaccessismadeforrefreshingpurposeonly,itwillmerelyrefreshthecontentsofthecells,notchangingthecontentsofthelatches.ItisnotnecessarytoprovideexternallygeneratedpulsesontheCASlinetoselectsuccessivecolumns.Thenecessarycontrolsignalsareprovidedinternallyusingacolumncounterandtheclocksignal.SDRAMshaveseveraldifferentmodesofoperation,whichcanbeselectedbywritingcontrolinformationintoamoderegister.SDRAMshavebuilt-inrefreshcircuitry.Arefreshcounterisapartofbuilt-inrefreshcircuitry.56SynchronousDRAMs(SDRAMs)BurstOperationTheburstoperationsusetheblocktransfercapability.Themoderegisterholdsa12-bitvaluethattheSDRAMlooksatinordertodeterminehowmanycolumnsitshouldBURSTandinwhatorderitshouldBURSTthem.Example:Burstreadoflength4inanSDRAMR/WRASCASClockFigure8.9.

Burstreadoflength4inanSDRAM.RowColD0D1D2D3AddressData58SynchronousDRAMs(SDRAMs)SpeedofSDRAMThespeedofSDRAMisratedinMHzratherthaninnanoseconds(ns).AdvantageThismakesiteasiertocomparethebusspeedandtheSDRAMchipspeed.ExampleIntelhasdefinedPC100andPC133busspecificationsinwhichthesystembusiscontrolledbya100or133MHzclockrespectively.Therefore,majormanufacturersofmemorychipsproduce100and133MHzSDRAMchips.

NoteConverttheSDRAMclockspeedtonanosecondsbydividingthechipspeedinto1billionns.59SynchronousDRAMs(SDRAMs)LatencyandBandwidth

LatencyandBandwidtharetwoparametersindicatingtheperformanceofamemorysystem.LatencyReferstotheamountoftimeittakestotransferawordofdatatoorfromthememory.NoteInblocktransfers,latencyisusedtodenotethetimeittakestotransferthefirstwordofdata.WhenbuyingDRAM,thelatencyratingthatyouseemostoftenisthememoryaccesstime.60SynchronousDRAMs(SDRAMs)LatencyandBandwidth

Example:Thefirstwordofdataistransferred5clockcycleslater.Thelatencyis5clockcycles.R/WRASCASClockFigure8.9.

Burstreadoflength4inanSDRAM.RowColD0D1D2D3AddressData61SynchronousDRAMs(SDRAMs)LatencyandBandwidth

BandwidthThenumberofbitsorbytesthatcanbetransferredinonesecondisreferredtoasbandwidth.Unit:bitpersecondorbytepersecondThebandwidthofamemoryunitdependsonthespeedofaccesstothestoreddataandonthenumberofbitsthatcanbeaccessedinparallel.Theeffectivebandwidthalsodependsonthetransfercapabilityofthelinksthatconnectthememoryandtheprocessor,typicallythespeedofthebus.EffectiveBandwidth=BusSpeed×BusWidth62SynchronousDRAMs(SDRAMs)Double-Data-RateSDRAM(DDRSDRAM)ItaccessesthecellarrayinthesamewaywithSDRAM,buttransferdataonbothedgesoftheclock.ThelatencyofthesedevicesisthesameasforstandardSDRAMs,andtheirbandwidthisessentiallydoubledforlongbursttransfers.NameClockFreq.DataRateDDR200100MHZ200MHZDDR266133MHZ266MHZDDR333167MHZ333MHZDDR400200MHZ400MHZ63SynchronousDRAMs(SDRAMs)DDR2SDRAM基于DDR技術(shù)，并在關(guān)鍵領(lǐng)域有所提升FBGApackage(更為良好的電氣性能與散熱性)4-bitprefetchbufferHigherlatency64FBGA(Fine-PitchBallGridArray,細(xì)間距球柵陣列)TSOP(ThinSmallOutlinepackage,薄型小尺寸封裝)65SynchronousDRAMs(SDRAMs)DDR3SDRAMComeswithapromiseofapowerconsumptionreductionof40%“Dual-gate”transistors(雙門電路晶體管):有兩個電子流輸入口，一個晶體管能輸入的電子流為原來的兩倍，從而提升了傳輸速度。

8bitpre-fetchbuffer66RambusDRAM(RDRAM)RambusTechnologyThekeyfeatureofRambustechnologyisafastsignalingmethodusedtotransferinformationbetweenchips.Insteadofusing0orVsupplytorepresentthelogicvalues0or1,thesignalsconsistofmuchsmallervoltageswings(differentialsignaling)aroundareferencevoltage,Vref.TheVrefisabout2V,thetwologicvaluesarerepresentedby0.3VswingsaboveorbelowVref.Smallvoltageswings=>

speedoftransmission.67StructureofLargerMemoriesStaticMemorySystemsHowtoconnectanumberofstaticmemorychipstoformamuchlargermemory?位擴展法

芯片每個存儲單元的位數(shù)小于存儲器字長，需進(jìn)行位擴展。例：用1M×1位存儲芯片組成1M×8位(1MB)的RAM共需8片1M×1位的芯片，每片存儲同一位權(quán)的一位數(shù)據(jù)(片的I/O端接Di)訪問芯片需20位地址碼A19~A0

讀寫控制信號WE688

I/O……A0D07I/O6I/O5I/O4I/O3I/O2I/O11Mⅹ1I/O中央處理器(CPU)數(shù)據(jù)總線地址總線D7A19WE69StructureofLargerMemoriesStaticMemorySystems字?jǐn)U展法芯片每個存儲單元的位數(shù)等于存儲器字長，但容量(字?jǐn)?shù))不夠，需進(jìn)行字?jǐn)U展。

例：用256K×8位芯片組成1MB的RAM共需1M/256K=4片256K×8位的芯片1MB容量需20位地址碼(A19~A0)，而256KB芯片需18位片內(nèi)地址碼(A17~A0)用高二位地址A19A18經(jīng)2:4譯碼器（74139）選擇芯片讀/寫每片8條I/O線分別接D7~D0

70256Kⅹ8

256Kⅹ8256Kⅹ8256Kⅹ82:4譯碼器A19A18A0A17D0~D7CPU01231234CSCSCSCS71StructureofLargerMemoriesStaticMemorySystems字位同時擴展法

單片芯片的字?jǐn)?shù)和位數(shù)均小于主存的容量要求，需進(jìn)行字、位的擴展。

例:

用512K×8位的存儲器芯片組成2M×32位的RAM。共需

片512K×8位的芯片ConclusionAssumethatthecapacityofamemoryunitisM×Nbit,ifconstitutedofusingl×kbitchips,thenumberoftotalchipsneededis(M/l)×(N/k).Figure8.10.Organizationofa2M32memorymoduleusing512K8staticmemorychips.19-bitinternalchipaddressChipselect

memorychipdecoder2-bitaddresses21-bit19-bitaddress512K8×A0A1A19

memorychipA20D31-24D7-0D23-16D15-8512K8×8-bitdatainput/output73StructureofLargerMemoriesStaticMemorySystems例:CPU的地址總線16根（A15~A0，A0為低位），雙向數(shù)據(jù)總線8根（D7~D0），控制總線中與主存有關(guān)的信號有（允許訪存，低電平有效），（高電平為讀命令，低電平為寫命令）。主存地址空間分配如下：0000H～3FFFH為系統(tǒng)程序區(qū)，由只讀存儲芯片組成；4000H～4FFFH為系統(tǒng)程序工作區(qū)，由SRAM組成；6000H～9FFFH為用戶程序區(qū)，也由SRAM組成。按字節(jié)編址?，F(xiàn)有如下存儲器芯片：EPROM：8K×8位（控制端僅有CS）SRAM：16K×1位，2K×8位，4K×8位，8K×8位請從上述芯片中選擇適當(dāng)芯片設(shè)計該計算機主存儲器，畫出主存儲器邏輯框圖，注意畫出選片邏輯（可選用門電路及3:8譯碼器74LS138）與CPU的連接，說明選哪些存儲器芯片及選多少片。74StructureofLargerMemoriesStaticMemorySystems【解】主存地址空間分布:0000H3FFFHFFFFH4FFFH9FFFH16KB(EPROM)4KB(SRAM)4KB(空)16KB(SRAM)24KB(空)4000H6000HA000H～～～～75......D0D7R/WA0A10A11A12A13A14A15MREQ7DAA80012EPROMDKBCS...D7D0A0A12SRAM8KBCS...D7D0A0A12SRAM8KBCS......D7D0A0A11SRAM4KBCS...D

7D0A0A12EPROM8KBCSR/WR/WY0Y1Y2Y3Y4Y5Y6Y7ABCG2BG2ACPU74LS138R/W76StructureofLargerMemoriesDynamicMemorySystemsTheorganizationoflargedynamicmemorysystemsisessentiallythesameastheabovestaticmemorysystem.SIMM(SingleIn-lineMemoryModules)ASIMMisabasicDRAMpackagingtypethatfitsmostoldersystems.ASIMMcanbeeithersingle-sided(withRAMchipsononesideonly)ordouble-sided(withRAMchipsonbothsides).30-pinSIMM:1-16MB;8bits;plus1bitforparity;single-sided72-pinSIMM:1MB,4MB,16MB(single-sided);2MB,8MB,32MB(double-sided);32bits,plus4bitsforparity/ECC.77StructureofLargerMemoriesDynamicMemorySystemsSIMM(SingleIn-lineMemoryModules)Example:Asingleinlinememorymodule(SIMM)holding32MB.TwoofthechipscontroltheSIMM.78StructureofLargerMemoriesDynamicMemorySystemsDIMM(DualIn-lineMemoryModules)Atpresent,DIMMsarethestandardwayformemorytobepackaged.ADIMMiscapableofdelivering64databitsatonce.MostcommontypesofDIMMs72-pin,144-pin,200-pinDIMMs:usedforSO-DIMM(SmallOutlineDIMM)168-pinDIMMs,usedforFPM(FastPageMode)DRAM,EDO(ExtendedDataOut)DRAM,andSDRAM184-pinDIMMs,usedforDDRSDRAM240-pinDIMMs,usedforDDR2SDRAM79StructureofLargerMemoriesDynamicMemorySystemsDIMM(DualIn-lineMemoryModules)Example:TwotypesofDIMMs:a168-pinSDRAMmodule(top)anda184-pinDDRSDRAMmodule(bottom).80StructureofLargerMemoriesDynamicMemorySystemsRIMM(RambusIn-lineMemoryModules)81MemorySystemConsiderationsTheChoiceofaRAMChipForagivenapplication,considerfollowingfactorsCostSpeedPowerdissipationSizeofthechipStaticRAMs:mostlyusedincachememoriesDynamicRAMs:Predominantchoiceforimplementingcomputermainmemories.82MemorySystemConsiderationsM