江蘇大學(xué)VHDL報(bào)告

二辣大亨夕JIANGSUUNIVERSITY課程實(shí)驗(yàn)報(bào)告電子設(shè)計(jì)自動(dòng)化實(shí)驗(yàn)報(bào)告學(xué)院班級學(xué)院班級學(xué)號電氣信息工程學(xué)院2015年10月實(shí)驗(yàn)一半加器和全加器的設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康氖煜ax+plusII軟件的作用學(xué)習(xí)用圖形輸入方式和VHDL語言輸入方式設(shè)計(jì)數(shù)字電路二、實(shí)驗(yàn)容圖形輸入方式設(shè)計(jì)半加器VHDL方式設(shè)計(jì)半加器libraryieee；useieee.std_logic_1164.all；entityhalf_adder11isport(a,b:instd_logic；so,co:outstd_logic)；endentityhalf_adder11；architecturefh1ofhalf_adder11isbeginso<=(axorb)；co<=(aandb)；endarchitecturefhl；圖形輸入方式設(shè)計(jì)全加器VHDL方式設(shè)計(jì)全加器libraryieee;useieee.std_logic_1164.all;entityor1isport(a,b:instd_logic;c:outstd_logic);endentityor1;architecturefu1ofor1isbeginc<=aorb;endarchitecturefu1;libraryieee;useieee.std_logic_1164.all；entityh_aisport(a,b:instd_logic；so,co:outstd_logic);endentityh_a；architecturefh1ofh_aisbeginso<=(axorb);co<=(aandb);endarchitecturefh1;libraryieee;useieee.std_logic_1164.all;entityfull_adder11isport(ain,bin,cin:instd_logic;cout,sum:outstd_logic);endentityfull_adder11;architecturefd1offull_adder11iscomponenth_aport(a,b:instd_logic;co,so:outstd_logic);endcomponent;componentor1port(a,b:instd_logic；c:outstd_logic)；endcomponent；signald,e,f:std_logic;beginu1:h_aportmap(a=>ain,b=>bin,co=>d,so=>e);u2:h_aportmap(a=>e,b=>cin,co=>f,so=>sum);u3:or1portmap(a=>d,b=>f,c=>cout);endarchitecturefd1;三、設(shè)計(jì)實(shí)現(xiàn)圖形輸入方式設(shè)計(jì)半加器VHDL方式設(shè)計(jì)半加器圖形輸入方式設(shè)計(jì)全加器VHDL方式設(shè)計(jì)全加器

COUTSUM四、仿真波形COUTSUM實(shí)驗(yàn)二四選一數(shù)據(jù)選擇器的設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康氖煜ax+plusII軟件的作用學(xué)習(xí)用圖形輸入方式和VHDL語言輸入方式設(shè)計(jì)數(shù)字電路二、實(shí)驗(yàn)容1?If語句libraryieee；useieee.std_logic_1164.all；entitymux41aisport(a,b,c,d:instd_logic_vector(3downto0)；sel:instd_logic_vector(1downto0)；y:outstd_logic_vector(3downto0))；endmux41a；architectureoneofmux41aisbeginprocess(a,b,c,d,sel)beginif(sel="00”)theny〈二a；elsif(sel="01”)theny<=b；elsif(sel="10”)theny<=c；elsif(sel="11”)theny<=d；endif；endprocess；endone；2.case語句useieee.std_logic_1164.all；entitymux41bisport(a,b,c,d:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);y:outstd_logic_vector(3downto0))；endmux41b;architectureoneofmux41bisbeginprocess(a,b,c,d,sel)begincaseseliswhen"00"=>y<=a;when"01"=>y<=b;when"10"=>y<=c;when"11"=>y<=d;whenothers=>y〈=null;endcase;endprocess;endone;3.when???else語句useieee.std_logic_1164.all；entitymux41cisport(a,b,c,d:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);y:outstd_logic_vector(3downto0))；endmux41c;architectureoneofmux41cisbeginy<=awhensel="00"elsebwhensel="01"elsecwhensel="10"elsedwhensel="11";endone;4.with.??select.??when語句libraryieee;useieee.std_logic_1164.all;entitymux41disport(a,b,c,d:instd_logic_vector(3downto0);

y:outstd_logic_vector(3downto0))；endmux41d;architectureoneofmux41disbeginwithselselecty<=awhen"00”,bwhen"01”,cwhen"10”,dwhen"11”,nullwhenothers；endone；三、設(shè)計(jì)實(shí)現(xiàn)MUX41Afits62OE3

四、仿真波形日_劃代_樹＞您伽妣珥hIlk舫誦1U■:111如Nk1加IIE血世K1：1111111」林1括匕hL1111■UL3卜|：L1|1111勵(lì)HC\±\110[|iI111'，i1，.實(shí)驗(yàn)三可逆計(jì)數(shù)器的設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康氖煜ax+plusII軟件的作用學(xué)習(xí)用圖形輸入方式和VHDL語言輸入方式設(shè)計(jì)數(shù)字電路二、實(shí)驗(yàn)容libraryieee；useieee.std_logic_1164.all；useieee.std_logic_unsigned.all;entitybicntisport(clk,rst,dir:instd_logic;q:bufferstd_logic_vector(3downto0));endbicnt;architectureoneofbicntisbeginprocess(clk,rst,dir)beginifrst='1'thenq<="0000”;elsif(clk'eventandclk二T)thenifdir='0'thenq〈=q+1;elseq<=q-1;endif;endif;endprocess;endone;三、設(shè)計(jì)實(shí)現(xiàn)