數(shù)字邏輯設(shè)計(jì)及應(yīng)用教學(xué)課件：3-1數(shù)字電路中的電氣知識(shí)

1、class-exercises1、Write the 8421 binary- coded decimal , Gray code,excess-3 representations for the decimal numbers: 5862、Indicate whether or not overflow occurs when adding the following 8-bit twos complement numbers: 1101 0100+ 1010 1011 0010 0110+ 0101 10101class-exercises1、Write the 8421 binary-

2、coded decimal ,excess-3 ,Gray code representations for the decimal numbers: 586.010110000110, 100010111001,11011011112、Indicate whether or not overflow occurs when adding the following 8-bit twos complement numbers: 1101 0100+ 1010 1011 0010 0110+ 0101 1010overflowoverflow2c h a p t e r 3 Digital Ci

3、rcuits數(shù)字電路electrical aspects of digital circuits數(shù)字電路中的電氣知識(shí)3reviewPositive logic and nagitive-logic (正邏輯和負(fù)邏輯)Three basic logics：AND,OR, and NOTMethod:(方法)Truth table 真值表Logic expression 邏輯表達(dá)式Logic symbol 邏輯符號(hào)NAND and NOR (與非和或非)Timing diagram 定時(shí)圖VOUTVINVccR獲得高、低電平的基本原理43.2 Logic Families(邏輯系列) A logi

4、c family is a collection of different integrated-circuit chips that have similar input, output, and internal circuit characteristics, but that perform different logic functions . Chips from the same family can be interconnected to perform any desired logic function. On the other hand, chips from dif

5、fering families may not be compatible; they may use different power-supply voltages or may use different input and output conditions to represent logic values. 53.2 Logic Families (邏輯系列)(P85)1、transistor-transistor logic (TTL) （晶體管-晶體管邏輯）2、CMOS（互補(bǔ)MOS） MOS :metal-oxide semiconductor (金屬-氧化物半導(dǎo)體) compl

6、ementary MOS (CMOS) 速度更高，功耗更低。63.3 CMOS Logic DC供電電壓直流供電電壓在邏輯圖中被省略了，但它其實(shí)是連接在芯片的VCC引腳上的，而地則連接在GND 引腳上。電壓和地在內(nèi)部被分配給IC中的所有元素。73.3.1 CMOS Logic Levels CMOS邏輯電平 (P86)A typical CMOS logic circuit operates from a 5-volt power supply. 典型的CMOS邏輯電路在電源下工作！ （3.3V工作的CMOS稱為低電壓CMOS。）邏輯1（高）邏輯0（低）0.0V1.5V3.5V5.0V未定義邏

7、輯電平83.3.2 MOS Transistors (MOS晶體管)漏極 drain源極 source柵極 gateVgs+n溝道源極 source漏極 drain柵極 gate+Vgsp溝道Rds：壓控電阻 Vgs(Vgs0) 增加，則Rds減少）Vgs(Vgs0)減少，則Rds減少9 3.3.3 Basic CMOS Inverter Circuit (P88)基本的CMOS反相器電路 常開開關(guān)： 當(dāng)控制信號(hào)為高電平時(shí)，開關(guān)接通。（2） 常閉開關(guān)： 當(dāng)控制信號(hào)為高電平時(shí)，開關(guān)斷開。VoutVin=0Vin=1Vout10Inverter Circuit 倒相器結(jié)構(gòu)Vin=0，Vout=1

8、in=0out常閉常開VccGND11Inverter Circuit 倒相器結(jié)構(gòu)Vin=1，Vout=0in=1out常閉常開VccGND12VDD = +5.0VVOUTVINTpTnVCCAZCMOS inverter circuit (CMOS反相器)(P88)常閉常開常閉常開inP 溝道N溝道采用器件實(shí)現(xiàn)邏輯關(guān)系13VCCAZCMOS INVERTERVDD = +5.0VZABQ4Q1Q3CMOS 2-input NAND gate2輸入CMOS與非門(P90)Q214VCCAZCMOS INVERTERVDD = +5.0VZABCMOS 2-input NOR gate (CM

9、OS或非門)15VCCAZCMOS inverter VDD = +5.0VAZNoninverting Gate 非反相門(P93)取非再取非（CMOS緩沖器）16CMOS 2-INPUT AND GATE17使用與非門還是或非門？VDD = +5.0VZABCMOS NOR gateVDD = +5.0VZABQ4Q1Q3CMOS NAND gateQ218NAND VS. NOR(P92)CMOS NAND and NOR gates do not have identical performance. For a given silicon area, an n-channel tra

10、nsistor has lower “on” resistance than a p-channel transistor.Therefore, when transistors are put in series, k n-channel transistors have lower “on” resistance than do k p-channel ones. As a result, a k-input NAND gate is generally faster than and preferred over a k-input NOR gate.193.3.5 Fan-In(扇入)

11、(P92)The number of inputs that a gate can have in a particular logic family is called the logic familys fan-in. 20串聯(lián)晶體管導(dǎo)通電阻的可加性 限制了MOS門的扇入數(shù)VDD = +5.0VZABVDD = +5.0VZAB the fan-in of CMOS gates, typically to 6 for NAND gates. the fan-in of CMOS gates, typically to 4 for NOR gates.21 The additive “on”

12、 resistance of series transistors limits the fan-in of CMOS gates, typically to 4 for NOR gates and 6 for NAND gates.The total delay through a 4-input NAND, a 2-input NOR, and an inverter is typically less than the delay ofa one-level 8-input NAND circuit.22 EXERCISE23ANSWER KEY FOR EXERCISEAND-OR-I

13、NVERT (coms AOI )gate243.4 Electrical Behavior of CMOS Circuits CMOS電路的電氣特性(P96)Logic voltage levels. ( 邏輯電壓電平)DC noise margins(直流噪聲容限)Fanout.(扇出)Speed, Power consumption(速度、功耗)Noise, Electrostatic discharge(噪聲、靜電放電)Open-drain outputs. Three-state outputs (漏極開路輸出、三態(tài)輸出)253.5 CMOS Steady-State Electri

14、cal Behavior (P90)CMOS穩(wěn)態(tài)電氣特性263.5.1 Logic Levels and Noise Margins 邏輯電平和噪聲容限VDD = +5.0VVOUTVINTpTn0 1 0127CMOS邏輯系列（HC）電平規(guī)格高態(tài)不正常狀態(tài)低態(tài)VOLmaxVILmaxVIHminVOHminVCC0.1V地0.1V0.7VCC0.3VCC典型值：VCC=5V+10%, Figure 3-26 Logic levels andnoise margins for the HC-series CMOS logic family. vcc028直流噪聲容限（DC noise margin）多大的噪聲會(huì)使最壞輸出電壓被破壞得不可被輸入端識(shí)別.高態(tài)不正常狀態(tài)低態(tài)VOLmax=0.1VVILmax=1.35VVIHm