第章宏模塊庫

1、整理ppt3/22/20221整理ppt3/22/202227.1 LPM計(jì)數(shù)器模塊調(diào)用（宏應(yīng)從魔術(shù)棒加入，否則無功能程序）定制過程！整理ppt3/22/202237.1.2 LPM計(jì)數(shù)器程序與參數(shù)傳遞語句整理ppt3/22/202247.1 LPM計(jì)數(shù)器模塊調(diào)用7.1.2 LPM計(jì)數(shù)器程序與參數(shù)傳遞語句整理ppt整理ppt整理ppt整理ppt以譯碼器為例仿真以譯碼器為例仿真整理ppt以鎖相環(huán)為例以鎖相環(huán)為例整理ppt建立時(shí)鐘1.注意：復(fù)位是低電平有效高電平鎖定耗時(shí)4個(gè)時(shí)鐘才能建立輸出時(shí)鐘整理ppt建立時(shí)鐘1.相位鎖相環(huán)相位鎖相環(huán)選擇整理ppt整理ppt時(shí)鐘2的建立整理ppt整理ppt還有NC

2、O數(shù)控振蕩器，但需要購買整理pptmodule PLL_Top( clk,button,clk_reg,s_clk_reg,q_clk_reg,s_clk,q_clk,trig_clk );inputclk, button;outputs_clk, s_clk_reg;outputq_clk, q_clk_reg; output trig_clk, clk_reg; MyPLL m1 (.inclk0(clk), .c0(s_clk), .c1(q_clk), .c2(trig_clk); MyPLLReg m2 (.trig_clk(trig_clk), .clk(clk), .button

3、(button), .s_clk(s_clk), .q_clk(q_clk), .clk_reg(clk_reg), .s_clk_reg(s_clk_reg), .q_clk_reg(q_clk_reg); endmodule整理pptmodule MyPLLReg(trig_clk, / from PLL output c2 (100Mhz)clk, / from PCB clock (50Mhz)button, / reset signal for registerss_clk, / from PLL output c0 (12.5Mhz)q_clk, / from PLL output

4、 c1 (25Mhz)clk_reg,s_clk_reg,q_clk_reg); input button; input trig_clk;input clk;input s_clk,q_clk;output clk_reg, s_clk_reg, q_clk_reg; reg clk_reg, s_clk_reg, q_clk_reg;always (posedge s_clk) if(!button) s_clk_reg = 0; else s_clk_reg = s_clk_reg;always (posedge q_clk) if (!button) q_clk_reg = 0; else q_clk_reg = q_clk_reg;always (posedge trig_clk) if (!button) clk_reg = 0; else clk_reg = clk; endmodule整理ppt整理ppt建立一個(gè)乘法器整理ppt整理ppt整理ppt整