verilog設(shè)計(jì)一四位計(jì)數(shù)器

1、FPGA與硬件描述語言實(shí)驗(yàn)報(bào)告學(xué)院：信息技術(shù)學(xué)院班級(jí)：專業(yè)：電子信息科學(xué)與技術(shù)姓名：日期：學(xué)號(hào)：1. 實(shí)驗(yàn)?zāi)康?、 熟悉行為級(jí)語法；2、 熟悉有限狀態(tài)機(jī)2.1實(shí)驗(yàn)內(nèi)容設(shè)計(jì)一四位計(jì)數(shù)器，進(jìn)行仿真，并檢測(cè)輸出結(jié)果；提示：在時(shí)鐘上升沿，如果復(fù)位信號(hào)有效，則復(fù)位為0,如果復(fù)位信號(hào)無效，則計(jì)數(shù)器需要加一。2.2實(shí)驗(yàn)內(nèi)容完成一個(gè)序列信號(hào)電路檢測(cè)器，檢測(cè)信號(hào)為10010，當(dāng)檢測(cè)到此序列時(shí)輸出端口輸出高電平，其余時(shí)間輸出低電平。提示：先畫出狀態(tài)轉(zhuǎn)換圖或?qū)懗鰻顟B(tài)轉(zhuǎn)換表，根據(jù)狀態(tài)表或者狀態(tài)圖完成代碼的設(shè)計(jì)；編寫測(cè)試模塊對(duì)該功能模塊進(jìn)行仿真。要求實(shí)驗(yàn)報(bào)告包括完整的狀態(tài)轉(zhuǎn)化圖或者轉(zhuǎn)化表。3實(shí)驗(yàn)記錄序列信號(hào)電路檢測(cè)器：

2、3.1功能塊代碼module mian (z, x, clock, clear); output z; reg z; input clock, clear; input x; parameter s0 = 3'd0, s1 = 3'd1, s2 = 3'd2, s3 = 3'd3, s5 = 3'd5, s4 = 3'd4; reg 2:0 state; reg 2:0 next_state; always (posedge clock) if(clear) state <= s0; else state <= next_state;

3、 always (state) begin case(state) s0: show = 0; s1: show = 0; s2: show = 0; s3: show = 0; s4: show = 0; s5: show = 1; endcase end always (x or state) begin case(state) s0: if(x = 0) next_state = s0; else next_state = s1; s1: if(x = 0) next_state = s2; else next_state = s1; s2: if(x = 0) next_state =

4、 s3; else next_state = s1; s3: if(x = 0) next_state = s0; else next_state = s4; s4: if(x = 0) next_state = s5; else next_state = s1; s5: if(x = 0) next_state = s0; else next_state = s1; endcase endendmodule3.2測(cè)試模塊代碼module stimulus_mv; wire z; reg x; reg clock, clear; mianMVP(z, x, clock, clear); ini

5、tial begin clock = 0; forever #5 clock = clock; end initial begin clear = 1; repeat(2)(negedge clock); clear = 0; end initial begin #30 x = 1; #10 x = 0; #10 x = 0; #10 x = 1; #10 x = 0; endendmodule 3.3仿真結(jié)果：1. 輸出：四位計(jì)數(shù)器3.1功能塊代碼module counter(out, clock, clear); output out; input clock, clear; reg 3:

6、0 out; always (posedge clock or negedge clear) begin if(clear) out <= 4'd0; else out <= out + 1; endendmodule3.2測(cè)試模塊代碼module counter_stimulus; reg clock, clear; wire 3:0 out; initial $monitor($time, "count = %b , clear = %b", out3:0, clear); counter MVP(out, clock, clear); always begin clear = 1'b1; #15 clear = 1'b0; #200 clear = 1'b1; #50 clear = 1'b1; end initial begin clock = 1'b0; forever